Analytical energy dissipation models for low-power caches
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Cycle-accurate simulation of energy consumption in embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Reducing leakage in a high-performance deep-submicron instruction cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Power Aware Design Methodologies
Power Aware Design Methodologies
Design Challenges of Technology Scaling
IEEE Micro
IEEE Transactions on Parallel and Distributed Systems
Performance Evaluation of the Multimedia Router with MPEG-2 Video Traffic
CANPC '99 Proceedings of the Third International Workshop on Network-Based Parallel Computing: Communication, Architecture, and Applications
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers
HOTI '02 Proceedings of the 10th Symposium on High Performance Interconnects HOT Interconnects
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Performance Enhancement Techniques for InfiniBand" Architecture
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Evaluating Run-Time Techniques for Leakage Power Reduction
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Power constrained design of multiprocessor interconnection networks
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Low-power system-level design of VLSI packet switching fabrics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A case for dynamic frequency tuning in on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Energy optimization schemes in cluster with virtual machines
Cluster Computing
RAFT: A router architecture with frequency tuning for on-chip networks
Journal of Parallel and Distributed Computing
EnergySaving cluster roll: power saving system for clusters
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
A survey on techniques for improving the energy efficiency of large-scale distributed systems
ACM Computing Surveys (CSUR)
Hi-index | 14.98 |
Designing energy-efficient clusters has recently become an important concern to make these systems economically attractive for many applications. Since the cluster interconnect is a major part of the system, the focus of this paper is to characterize and optimize the energy consumption in the entire interconnect. Using a cycle-accurate simulator of an InfiniBand Architecture (IBA) compliant interconnect fabric and actual designs of its components, we investigate the energy behavior on regular and irregular interconnects. The energy profile of the three major components (switches, network interface cards (NICs), and links) reveals that the links and switch buffers consume the major portion of the power budget. Hence, we focus on energy optimization of these two components. To minimize power in the links, first we investigate the dynamic voltage scaling (DVS) algorithm and then propose a novel dynamic link shutdown (DLS) technique. The DLS technique makes use of an appropriate adaptive routing algorithm to shut down the links intelligently. We also present an optimized buffer design for reducing leakage energy in 70nm technology. Our analysis on different networks reveals that, while DVS is an effective energy conservation technique, it incurs significant performance penalty at low to medium workload. Moreover, energy saving with DVS reduces as the buffer leakage current becomes significant with 70nm design. On the other hand, the proposed DLS technique can provide optimized performance-energy behavior (up to 40 percent energy savings with less than 5 percent performance degradation in the best case) for the cluster interconnects.