Low power system scheduling and synthesis

  • Authors:
  • Niraj K. Jha

  • Affiliations:
  • Princeton University, Princeton, NJ

  • Venue:
  • Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
  • Year:
  • 2001

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Abstract

Many scheduling techniques have been presented recently which exploit dynamic voltage scaling (DVS) and dynamic power management (DPM) for both uniprocessors and distributed systems, as well as both real-time and non-real-time systems. While such techniques are power-aware and aim at extending battery lifetimes for portable systems, they need to be augmented to make them battery-aware as well. We will survey such power-aware and battery-aware scheduling algorithms. Also, system synthesis algorithms for real-time systems-on-a-chip (SOCs), distributed and wireless client-server embedded systems, etc., have begun optimizing power consumption in addition to system price. We will survey such algorithms as well, and point out some open problems.