Power optimization of real-time embedded systems on variable speed processors

  • Authors:
  • Youngsoo Shin;Kiyoung Choi;Takayasu Sakurai

  • Affiliations:
  • University of Tokyo, Tokyo 106-8558, Japan;Seoul National University, Seoul 151-742, Korea;University of Tokyo, Tokyo 106-8558, Japan

  • Venue:
  • Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
  • Year:
  • 2000

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Abstract

Power efficient design of real-time embedded systems based on programmable processors becomes more important as system functionality is increasingly realized through software. This paper presents a power optimization method for real-time embedded applications on a variable speed processor. The method combines off-line and on-line components. The off-line component determines the lowest possible maximum processor speed while guaranteeing deadlines of all tasks. The on-line component dynamically varies the processor speed or bring a processor into a power-down mode according to the status of task set in order to exploit execution time variations and idle intervals. Experimental results show that the proposed method obtains a significant power reduction across several kinds of applications.