Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Low-power operation using self-timed circuits and adaptive scaling of the supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Design Automation for Embedded Systems
Processor design for portable systems
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
Data driven signal processing: an approach for energy efficient computing
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Voltage scheduling problem for dynamically variable voltage processors
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Digital Signal Processing in Communication Systems
Digital Signal Processing in Communication Systems
Power optimization of real-time embedded systems on variable speed processors
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Rapid prototyping for wireless designs: the five-ones approach
Signal Processing - From signal processing theory to implementation
Automated Floating-Point to Fixed-Point Conversion with the Fixify Environment
RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
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During recent years power optimisation has become one of the most challenging design goals in modern communication systems, particularly in the wireless domain. Many different approaches for task scheduling on single or multi-core systems exist, mostly addressing the minimisation of execution time or the number of processors used. The minimisation of the processor's clock frequency by adjusting the supply voltage or directly by frequency scaling according to the chosen task scheduling has shown good results in the reduction of power consumption. Most of the known approaches base their core algorithms on graph representations for multi-rate systems or synchronous data flow (SDF) graphs, in a single frequency domain. In many cases a signal processing system comprises several frequency domains, in which processes have to be fired according to their in- and output data rates as well as to their frequency domain. In this work the superposition of frequency domains and data dependencies is incorporated into the optimisation process and used as a another degree of freedom. Several algorithms have been implemented and evaluated to minimise the required processor's clock frequency, including a greedy, a simulated annealing, as well as a tabu search approach.