Real-time dynamic voltage scaling for low-power embedded operating systems
SOSP '01 Proceedings of the eighteenth ACM symposium on Operating systems principles
Critical power slope: understanding the runtime effects of frequency scaling
ICS '02 Proceedings of the 16th international conference on Supercomputing
Process cruise control: event-driven clock scaling for dynamic power management
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Power optimization of real-time embedded systems on variable speed processors
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A scheduling model for reduced CPU energy
FOCS '95 Proceedings of the 36th Annual Symposium on Foundations of Computer Science
Performance Comparison of Dynamic Voltage Scaling Algorithms for Hard Real-Time Systems
RTAS '02 Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02)
Dynamic and Aggressive Scheduling Techniques for Power-Aware Real-Time Systems
RTSS '01 Proceedings of the 22nd IEEE Real-Time Systems Symposium
Leakage aware dynamic voltage scaling for real-time embedded systems
Proceedings of the 41st annual Design Automation Conference
Procrastination scheduling in fixed priority real-time systems
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Dynamic slack reclamation with procrastination scheduling in real-time embedded systems
Proceedings of the 42nd annual Design Automation Conference
Handbook of Real-Time and Embedded Systems
Handbook of Real-Time and Embedded Systems
Variable voltage scheduling with the priority-based functional reactive programming language
Proceedings of the 2013 Research in Adaptive and Convergent Systems
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In the past decades, many algorithms with the goal of achieving energy efficiency have been proposed for scheduling real-time tasks. Due to a lack of a unified testing framework, most of them were evaluated via simulations under their own experimental scenarios. However, finding their performance in real processors is essential if these algorithms are to be used in practice. In this paper, we design a unified framework to evaluate power-aware scheduling algorithms based on a real Intel PXA255 XScale processor, and present a case study to compare several key algorithms using DVS/Shut-Down. The energy efficiency and the quantitative difference in their performance as well as the practical issues found in the implementation of these algorithms are discussed. Our experiments show a gap between the theoretical results and the real results. Our framework not only gives researchers a tool to evaluate their system designs, but also helps them to bridge this gap in their future works.