REYSM, a high performance, low power multi-processor bus
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Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
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FAST: Frequency-Aware Static Timing Analysis
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Power minimization techniques on distributed real-time systems by global and local slack management
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OSDI '94 Proceedings of the 1st USENIX conference on Operating Systems Design and Implementation
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Execution time for realtime processes running on multiprocessor system-on-chip platform varies due to the contention on the bus. Considering the worst case execution cycles necessitates over-clocking the system to meet the realtime deadlines, which has a negative impact on the system power requirements. For periodic applications coscheduled on multiprocessor with shared bus, the cycles needed by a memory transaction fluctuate based on the execution overlap between processes' activities on bus. In this work, we show the effect on execution cycles of different scheduling overlap of processes. Experiments' results demonstrate that the execution cycles, and therefore the clock frequency, can be lowered by up to 24% on a 4 processor MPSoC. As the power consumption varies cubically with frequency, this reduction can lead to a significant power saving. Instead of exhaustively simulating all configurations to search for optimal scheduling overlap, we devise a scheme to predict the effect of scheduling. We propose the use of shift-variance of bus traffic profile of applications running individually on the system to predict the effect when scheduling these applications simultaneously. We show that the devised predictor of scheduling effect highly correlates to the behavior observed through simulations.