A portable global optimizer and linker
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Some Results of the Earliest Deadline Scheduling Algorithm
IEEE Transactions on Software Engineering
Predicting program execution times by analyzing static and dynamic program paths
Real-Time Systems - Special issue: Real-time languages and language-level timing tools and analysis
Combining static worst-case timing analysis and program proof
Real-Time Systems
Bounding Pipeline and Instruction Cache Performance
IEEE Transactions on Computers
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Timing Analysis for Data and Wrap-Around Fill Caches
Real-Time Systems
Timing Analysis for Instruction Caches
Real-Time Systems - Special issue on worst-case execution-time analysis
Hard real-time scheduling for low-energy using stochastic data and DVS processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Real-time dynamic voltage scaling for low-power embedded operating systems
SOSP '01 Proceedings of the eighteenth ACM symposium on Operating systems principles
Energy-conserving feedback EDF scheduling for embedded systems with real-time constraints
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Integrating the timing analysis of pipelining and instruction caching
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Cache modeling for real-time software: beyond direct mapped instruction caches
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Virtual simple architecture (VISA): exceeding the complexity limit in safe real-time systems
Proceedings of the 30th annual international symposium on Computer architecture
Dynamic and Aggressive Scheduling Techniques for Power-Aware Real-Time Systems
RTSS '01 Proceedings of the 22nd IEEE Real-Time Systems Symposium
The effects of energy management on reliability in real-time embedded systems
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
FAST: Frequency-aware static timing analysis
ACM Transactions on Embedded Computing Systems (TECS)
Energy management for real-time embedded systems with reliability requirements
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A design framework for real-time embedded systems with code size and energy constraints
ACM Transactions on Embedded Computing Systems (TECS)
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC
Transactions on High-Performance Embedded Architectures and Compilers II
Minimizing CPU energy in real-time systems with discrete speed management
ACM Transactions on Embedded Computing Systems (TECS)
A power aware study for VTDIRECT95 using DVFS
SpringSim '09 Proceedings of the 2009 Spring Simulation Multiconference
Coscheduling of processor voltage and control task period for energy-efficient control systems
ACM Transactions on Embedded Computing Systems (TECS)
Energy-aware packet and task co-scheduling for embedded systems
EMSOFT '10 Proceedings of the tenth ACM international conference on Embedded software
Parametric timing analysis and its application to dynamic voltage scaling
ACM Transactions on Embedded Computing Systems (TECS)
Energy efficient configuration for qos in reliable parallel servers
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
Effective dynamic voltage scaling through CPU-Boundedness detection
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
Speed scaling problems with memory/cache consideration
TAMC'12 Proceedings of the 9th Annual international conference on Theory and Applications of Models of Computation
Optimization power consumption model of reliability-aware GPU clusters
The Journal of Supercomputing
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Power is a valuable resource in embedded systems asthe lifetime of many such systems is constrained by theirbattery capacity. Recent advances in processor design haveadded support for dynamic frequency/voltage scaling (DVS)for saving power. Recent work on real-time scheduling focuseson saving power in static as well as dynamic schedulingenvironments by exploiting idle and slack due to earlytask completion for DVS of subsequent tasks. These schedulingalgorithms rely on a prioriknowledge of worst-case executiontimes (WCET) for each task. They assume that DVShas no effect on the worst-case execution cycles (WCEC)of a task and scale the WCET according to the processorfrequency. However, for systems with memory hierarchies,the WCEC typically does change under DVS due tofrequency modulation. Hence, current assumptions used byDVS schemes result in a highly exaggerated WCET.This paper contributes novel techniques for tight andflexible static timing analysis particularly well-suited fordynamic scheduling schemes. The technical contributionsare as follows: (1) We assess the problem of changing executioncycles due to scaling techniques. (2) We proposea parametric approach towards bounding the WCET staticallywith respect to the frequency. Using a parametricmodel, we can capture the effect of changes in frequencyon the WCEC and, thus, accurately model the WCET overany frequency range. (3) We discuss design and implementationof the frequency-aware static timing analysis (FAST)tool based on our prior experience with static timing analysis.(4) We demonstrate in experiments that our FAST toolprovides safe upper bounds on the WCET, which are tight.The FAST tool allows us to capture the WCET of six benchmarksusing equations that overestimate the WCET by lessthan 1%. FAST equations can also be used to improve existingDVS scheduling schemes to ensure that the effect of frequencyscaling on WCET is considered and that the WCETused is not exaggerated. (5) We leverage three DVS schedulingschemes by incorporating FAST into them and by showingthat the power consumption further decreases. To thebest of our knowledge, this study of DVS effects on timinganalysis is unprecedented.