Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
A portable global optimizer and linker
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Calculating the maximum, execution time of real-time programs
Real-Time Systems
Predicting program execution times by analyzing static and dynamic program paths
Real-Time Systems - Special issue: Real-time languages and language-level timing tools and analysis
Pipelined processors and worst case execution times
Real-Time Systems
Fixed priority pre-emptive scheduling: an historical perspective
Real-Time Systems - Special issue: history of real-time systems
Static cache simulation and its applications
Static cache simulation and its applications
Bounding worst-case data cache performance
Bounding worst-case data cache performance
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Bounding Pipeline and Instruction Cache Performance
IEEE Transactions on Computers
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Optimizing Supercompilers for Supercomputers
Optimizing Supercompilers for Supercomputers
Parallel Programming and Compilers
Parallel Programming and Compilers
High Performance Compilers for Parallel Computing
High Performance Compilers for Parallel Computing
Efficient worst case timing analysis of data caching
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Timing Analysis for Data Caches and Set-Associative Caches
RTAS '97 Proceedings of the 3rd IEEE Real-Time Technology and Applications Symposium (RTAS '97)
Worst case timing analysis of RISC processors: R3000/R3010 case study
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Efficient microarchitecture modeling and path analysis for real-time software
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Integrating the timing analysis of pipelining and instruction caching
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Cache modeling for real-time software: beyond direct mapped instruction caches
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Virtual simple architecture (VISA): exceeding the complexity limit in safe real-time systems
Proceedings of the 30th annual international symposium on Computer architecture
FAST: Frequency-Aware Static Timing Analysis
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Compositional static instruction cache simulation
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Improving WCET by applying a WC code-positioning optimization
ACM Transactions on Architecture and Code Optimization (TACO)
FAST: Frequency-aware static timing analysis
ACM Transactions on Embedded Computing Systems (TECS)
Improving WCET by applying worst-case path optimizations
Real-Time Systems
Timing analysis for preemptive multitasking real-time systems with caches
ACM Transactions on Embedded Computing Systems (TECS)
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Towards Time-Predictable Data Caches for Chip-Multiprocessors
SEUS '09 Proceedings of the 7th IFIP WG 10.2 International Workshop on Software Technologies for Embedded and Ubiquitous Systems
Parametric timing analysis and its application to dynamic voltage scaling
ACM Transactions on Embedded Computing Systems (TECS)
Tightening the bounds on feasible preemptions
ACM Transactions on Embedded Computing Systems (TECS)
Data cache organization for accurate timing analysis
Real-Time Systems
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Thecontributions of this paper are twofold. First, an automatictool-based approach is described to bound worst-case data cacheperformance. The approach works on fully optimized code, performsthe analysis over the entire control flow of a program, detectsand exploits both spatial and temporal locality within data references,and produces results typically within a few seconds. Resultsobtained by running the system on representative programs arepresented and indicate that timing analysis of data cache behaviorusually results in significantly tighter worst-case performancepredictions. Second, a method to deal with realistic cache fillingapproaches, namely wrap-around-filling for cache misses, is presentedas an extension to pipeline analysis. Results indicate that worst-casetiming predictions become significantly tighter when wrap-around-fillanalysis is performed. Overall, the contribution of this paperis a comprehensive report on methods and results of worst-casetiming analysis for data caches and wrap-around caches. The approachtaken is unique and provides a considerable step toward realisticworst-case execution time prediction of contemporary architecturesand its use in schedulability analysis for hard real-time systems.