Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemptive Scheduling
IEEE Transactions on Computers
Bounding Pipeline and Instruction Cache Performance
IEEE Transactions on Computers
Efficient and Precise Cache Behavior Prediction for Real-TimeSystems
Real-Time Systems
Timing Analysis for Data and Wrap-Around Fill Caches
Real-Time Systems
Guest Editorial: A Review of Worst-Case Execution-TimeAnalysis
Real-Time Systems - Special issue on worst-case execution-time analysis
Timing Analysis for Instruction Caches
Real-Time Systems - Special issue on worst-case execution-time analysis
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Efficient longest executable path search for programs with complex flows and pipeline effects
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Associative caches in formal software timing analysis
Proceedings of the 39th annual Design Automation Conference
Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Approximation of Worst-Case Execution Time for Preemptive Multitasking Systems
LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Data cache locking for higher program predictability
SIGMETRICS '03 Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Virtual simple architecture (VISA): exceeding the complexity limit in safe real-time systems
Proceedings of the 30th annual international symposium on Computer architecture
Clustered calculation of worst-case execution times
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Data Caches in Multitasking Hard Real-Time Systems
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Compositional static instruction cache simulation
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
A time-predictable execution mode for superscalar pipelines with instruction prescheduling
Proceedings of the 2nd conference on Computing frontiers
Clustered Worst-Case Execution-Time Calculation
IEEE Transactions on Computers
Worst case execution time analysis for synthesized hardware
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Data cache locking for tight timing calculations
ACM Transactions on Embedded Computing Systems (TECS)
Tightening the bounds on feasible preemptions
ACM Transactions on Embedded Computing Systems (TECS)
Modeling complex flows for worst-case execution time analysis
RTSS'10 Proceedings of the 21st IEEE conference on Real-time systems symposium
Cache-related preemption delay via useful cache blocks: Survey and redefinition
Journal of Systems Architecture: the EUROMICRO Journal
To cache or not to cache: the effects of warming cache in complex SPARQL queries
OTM'11 Proceedings of the 2011th Confederated international conference on On the move to meaningful internet systems - Volume Part II
Data cache organization for accurate timing analysis
Real-Time Systems
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Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching. However there has not been much progress in worst case timing analysis of data caching. This is mainly due to load/store instructions that reference multiple memory locations such as those used to implement array and pointer based references. These load/store instructions are called dynamic load/store instructions and most current analysis techniques take a very conservative approach to their timing analysis. In many cases, it is assumed that each of the references from a dynamic load/store instruction will miss in the cache and replace a cache block that would otherwise lead to a cache hit. This conservative approach results in severe overestimation of the worst case execution time (WCET). The paper proposes two techniques to minimize the WCET overestimation due to such load/store instructions. The first technique uses a global data flow analysis technique to reduce the number of load/store instructions that are misclassified as dynamic load/store instructions. The second technique utilizes data dependence analysis to minimize the adverse impact of dynamic load/store instructions. The paper also compares the WCET bounds of simple benchmark programs that are predicted with and without applying the proposed techniques. The results show that they significantly (up to 20%) improve the accuracy of WCET estimation especially for programs with a large number of references from dynamic load/store instructions.