Worst case execution time analysis for synthesized hardware

Authors:
Jun-hee Yoo;Xingguang Feng;Kiyoung Choi;Eui-young Chung;Kyu-Myung Choi
Affiliations:
Seoul National University, Seoul, Republic of Korea;Seoul National University, Seoul, Republic of Korea;Seoul National University, Seoul, Republic of Korea;Samsung Electronics, Yongin, Republic of Korea;Samsung Electronics, Yongin, Republic of Korea
Venue:
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Year:
2006

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Abstract

We propose a hardware performance estimation flow for fast design space exploration, based on worst-case execution time analysis algorithms for software analysis. Test cases on some real-world applications show that our flow provides a tight upper bound of the execution time, and many useful hints to the designer.