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Statecharts: A visual formalism for complex systems
Science of Computer Programming
Performance estimation of embedded software with instruction cache modeling
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Compile-Time Scheduling of Dynamic Constructs in Dataflow Program Graphs
IEEE Transactions on Computers
Embedded program timing analysis based on path clustering and architecture classification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Communication estimation for hardware/software codesign
Proceedings of the 6th international workshop on Hardware/software codesign
A hardware-software cosynthesis technique based on heterogeneous multiprocessor scheduling
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
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Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Fast performance analysis of bus-based system-on-chip communication architectures
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
High-level synthesis under multi-cycle interconnect delay
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Hardware/software partitioning of embedded system in OCAPI-xl
Proceedings of the ninth international symposium on Hardware/software codesign
System level design with spade: an M-JPEG case study
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Process Partitioning for Distributed Embedded Systems
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
A New Approach to Solving the Hardware-Software Partitioning Problem in Embedded System Design
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
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IEEE Transactions on Computers
Constraint-driven bus matrix synthesis for MPSoC
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Worst case execution time analysis for synthesized hardware
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
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IEEE Transactions on Evolutionary Computation
IEEE Transactions on Evolutionary Computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical finite state machines with multiple concurrency models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
International Journal of Reconfigurable Computing
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ACM SIGARCH Computer Architecture News
Simulated annealing-based diffusive load balancing on many-core SoC
Proceedings of the 8th ACM international conference on Autonomic computing
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International Journal of High Performance Systems Architecture
Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs
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ACM Transactions on Architecture and Code Optimization (TACO)
Mapping on multi/many-core systems: survey of current and emerging trends
Proceedings of the 50th Annual Design Automation Conference
CADSE: communication aware design space exploration for efficient run-time MPSoC management
Frontiers of Computer Science: Selected Publications from Chinese Universities
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Time-to-market pressure and the ever-growing design complexity of multiprocessor system-on-chips have demanded an efficient design environment that enables fast exploration of large design space. In this article, we introduce a new design environment, called SoCDAL, for accelerating multiprocessor system-on-chip design through fast design-space exploration targeting real-time multimedia systems. SoCDAL is a set of mostly automated tools covering system specification, hardware/software estimation, application-to-architecture mapping, simulation model generation, and system verification through simulation. For system specification, the process network model has been widely used for system specification because of its modeling capability. However, it is hard to use for real-time systems design, since its behavior cannot be estimated statically. We introduce a new approach which enables analyzing a process network model statically with some restrictions. For the hardware/software estimation, we analyze codes statically. Application-to-architecture mapping process implements a novel algorithm to support an arbitrary number of processors, with performance evaluation by static scheduling considering communication behavior. Mapping results are used to generate simulation models automatically at several transaction levels to be pipelined to a commercial tool. We show the effectiveness of our approaches by some experimental results with multimedia applications such as JPEG, H.263, and H.264 encoders, as well as an H.264 decoder.