Specification and design of embedded systems
Specification and design of embedded systems
Performance analysis and optimization of schedules for conditional and loop-intensive specifications
DAC '94 Proceedings of the 31st annual Design Automation Conference
Synthesis of system-level communication by an allocation-based approach
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Communication synthesis for distributed embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Static timing analysis of embedded software
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '97 Proceedings of the 34th annual Design Automation Conference
Performance analysis of a system of communicating processes
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Embedded program timing analysis based on path clustering and architecture classification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
A case study on modeling shared memory access effects during performance analysis of HW/SW systems
Proceedings of the 6th international workshop on Hardware/software codesign
Integrating communication protocol selection with partitioning in hardware/software codesign
Proceedings of the 11th international symposium on System synthesis
Bus-based communication synthesis on system level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimizing communication in embedded system co-simulation
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Proceedings of the 37th Annual Design Automation Conference
On-chip communication architecture for OC-768 network processors
Proceedings of the 38th annual Design Automation Conference
Control and communication performance analysis of embedded DSP systems in the MASIC methodology
Proceedings of the 14th international symposium on Systems synthesis
Traffic analysis for on-chip networks design of multimedia applications
Proceedings of the 39th annual Design Automation Conference
Efficient exploration of the SoC communication architecture design space
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
System level design with spade: an M-JPEG case study
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Architecture-level performance evaluation of component-based embedded systems
Proceedings of the 40th annual Design Automation Conference
SystemC
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
On-chip traffic modeling and synthesis for MPEG-2 video applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Exploring SW Performance Using SoC Transaction-Level Modeling
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
NoCEE: energy macro-model extraction methodology for network on chip routers
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Performance guarantees by simulation of process
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
SoCDAL: System-on-chip design AcceLerator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Exploring design space using transaction level models
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
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This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based System-on-Chip (SOC) communication architectures. Our technique fills a gap in existing techniques for system-level performance analysis, which are either too slow to use in an iterative communication architecture design framework (e.g., simulation of the complete system), or are not accurate enough to drive the design of the communication architecture (e.g., techniques that perform a “static” analysis of the system performance). The proposed system-level performance analysis technique consists of (i) initial co-simulation performed after IIW/SW partitioning and mapping, with the communication between components modeled in an abstract manner (e.g., as events or data transfers), (ii) extraction of abstracted symbolic traces, represented as a Bus and Synchronization Event (BSE) Graph, that captures the activity of the various system components and their communication over time, and (iii) manipulation of the BSE Graph using the bus parameters, to derive the behavior of the system accounting for effects of the bus architecture. We present experimental results on several example systems, including a TCP/IP network interface card sub-system. The results indicate that our performance estimation technique is over two orders of magnitude faster than performing a complete system simulation, while being very accurate (within 2.2% of performance estimates derived from accurate HW/SW co-simulation).