Performance analysis and optimization of schedules for conditional and loop-intensive specifications
DAC '94 Proceedings of the 31st annual Design Automation Conference
Formulation and evaluation of scheduling techniques for control flow graphs
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Performance analysis of a system of communicating processes
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A case study on modeling shared memory access effects during performance analysis of HW/SW systems
Proceedings of the 6th international workshop on Hardware/software codesign
Fast performance analysis of bus-based system-on-chip communication architectures
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Standards for system-level design: practical reality or solution in search of a question?
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Hardware Software Codesign of DSP System Using Grammar Based Approach
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
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The time required by an embedded system to process information does not only depend on the amount of data; it also depends heavily on the synchronization overhead, bus protocol and communication architecture. This paper presents a technique to estimate the performance of the control and communication part of an embedded system modeled using the MASIC methodology. A key concept in MASIC is the strict separation of the computation part from the control and communication. Based on this clear separation of concerns the estimator analyzes the communication delay. Our method targets applications with intense, but regular data flow with a fair amount of complex control. Examples are base stations or mobile terminals. For these applications the method allows a cycle accurate estimation of the delay due to the communication. Hence, different architectures can be evaluated and e.g. the effect of different bus arbitration and different DMA block sizes can be assessed. Thus, the proposed method is an aid for the designer to explore the system with different system level decisions.