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EURO-DAC '92 Proceedings of the conference on European design automation
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DAC '94 Proceedings of the 31st annual Design Automation Conference
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DAC '96 Proceedings of the 33rd annual Design Automation Conference
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ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Fast true delay estimation during high level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A case study on modeling shared memory access effects during performance analysis of HW/SW systems
Proceedings of the 6th international workshop on Hardware/software codesign
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Proceedings of the 11th international symposium on System synthesis
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ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 14th international symposium on Systems synthesis
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Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
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SystemC
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DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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Efficient exploration of the system design space necessitates fast and accurate performance estimation as opposed to the computationally prohibitive alternative of exhaustive simulation. The paper addresses the issue of worst case performance analysis of a system described as a set of concurrent communicating processes. We show that the synchronization overhead associated with inter process communication can contribute significantly to the overall system performance. Application of existing performance analysis techniques, which target single process descriptions, lead to inaccurate performance estimates as the synchronization overhead is not accounted for. We present PERC, a fast and accurate worst case performance analysis technique which analyzes inter process communication, and accounts for synchronization overhead while computing the worst case performance estimate of a given system implementation. Application of PERC to example systems described as multiple communicating processes shows the ability of the proposed method to accurately estimate the worst case performance of the system implementation.