Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
High-level synthesis from VHDL with exact timing constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Synthesis of concurrent system interface modules with automatic protocol conversion generation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Software scheduling in the co-synthesis of reactive real-time systems
DAC '94 Proceedings of the 31st annual Design Automation Conference
Interface timing verification with application to synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
Scheduling using behavioral templates
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Behavioral synthesis methodology for HDL-based specification and validation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Interval scheduling: fine-grained code scheduling for embedded systems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Interfacing incompatible protocols using interface process generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An approach to interface synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Interface co-synthesis techniques for embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Communication synthesis for distributed embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Performance analysis of a system of communicating processes
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Automatic synthesis of interfaces between incompatible protocols
DAC '98 Proceedings of the 35th annual Design Automation Conference
Automated composition of hardware components
DAC '98 Proceedings of the 35th annual Design Automation Conference
Communication synthesis and HW/SW integration for embedded system design
Proceedings of the 6th international workshop on Hardware/software codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Surviving the SOC revolution: a guide to platform-based design
Surviving the SOC revolution: a guide to platform-based design
A practical tool box for system level communication synthesis
Proceedings of the ninth international symposium on Hardware/software codesign
Understanding Behavioral Synthesis: A Practical Guide to High-Level Design
Understanding Behavioral Synthesis: A Practical Guide to High-Level Design
Hardware-Software Co-Synthesis of Distributed Embedded Systems
Hardware-Software Co-Synthesis of Distributed Embedded Systems
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Protocol selection and interface generation for HW-SW codesign
Readings in hardware/software co-design
Validation in a component-based design flow for multicore SoCs
Proceedings of the 15th international symposium on System Synthesis
Algorithms for Interface Timing Verification
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Proceedings of the 40th annual Design Automation Conference
A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Model Refinement for Hardware-Software Codesign
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Design of an Optimal Loosely Coupled Heterogeneous Multiprocessor System
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Codesign Experiment in Acoustic Echo Cancellation: GMDFa
ISSS '96 Proceedings of the 9th international symposium on System synthesis
System Design for DSP Applications Using the MASIC Methodology
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A memory aware behavioral synthesis tool for real-time VLSI circuits
Proceedings of the 14th ACM Great Lakes symposium on VLSI
CODEF: a system level design space exploration tool
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
Integrating communication protocol selection with hardware/software codesign
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-level performance analysis for designing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A design methodology for space-time adapter
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Journal of Signal Processing Systems
Two iterative metaheuristic approaches to dynamic memory allocation for embedded systems
EvoCOP'11 Proceedings of the 11th European conference on Evolutionary computation in combinatorial optimization
A mathematical model and a metaheuristic approach for a memory allocation problem
Journal of Heuristics
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IP integration, which is one of the most important SoC design steps, requires taking into account communication and timing constraints. In that context, design and reuse can be improved using IP cores described at a high abstraction level. In this paper, we present an IP design approach that relies on three main phases: (1) constraint modeling, (2) IP constraint analysis steps for feasibility checking, and (3) synthesis. We propose a set of techniques dedicated to the digital signal processing domain that lead to an optimized IP core integration. Based on a generic architecture of components, the method we propose provides automatic generation of IP cores designed under integration constraints. We show the effectiveness of our approach with a DCT core design case study.