IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A practical tool box for system level communication synthesis
Proceedings of the ninth international symposium on Hardware/software codesign
A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Proceedings of the 41st annual Design Automation Conference
Efficient On-Chip Communications for Data-Flow IPs
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
Synchronization Processor Synthesis for Latency Insensitive Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3)
Proceedings of the 42nd annual Design Automation Conference
A formal method for hardware IP design and integration under I/O and timing constraints
ACM Transactions on Embedded Computing Systems (TECS)
Buffer memory optimization for video codec application modeled in Simulink
Proceedings of the 43rd annual Design Automation Conference
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This paper presents a solution to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. By explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named Space-Time AdapteR (STAR). Our design flow inputs a C description of Input/Output data scheduling, and user requirements (throughput, latency, parallelism&), and formalizes communication constraints through a Resource Constraints Graph (RCG). The RCG properties enable an efficient architecture space exploration in order to synthesize a STAR component. The proposed approach has been tested to design an industrial data mixing block example: an Ultra-Wideband interleaver.