A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3)

Authors:
P. Urard;L. Paumier;P. Georgelin;T. Michel;V. Lebars;E. Yeo;B. Gupta
Affiliations:
STMicroelectronics, San Jose, CA;STMicroelectronics, San Jose, CA;STMicroelectronics, San Jose, CA;STMicroelectronics, San Jose, CA;STMicroelectronics, San Jose, CA;STMicroelectronics, San Jose, CA;W5Networks, Palo Alto, CA
Venue:
Proceedings of the 42nd annual Design Automation Conference
Year:
2005

Citing 2
Cited 5

Computer-Aided Reasoning: An Approach

Computer-Aided Reasoning: An Approach
A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3)

Proceedings of the 42nd annual Design Automation Conference

A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3)

Proceedings of the 42nd annual Design Automation Conference
Low cost LDPC decoder for DVB-S2

Proceedings of the conference on Design, automation and test in Europe: Designers' forum
A design methodology for space-time adapter

Proceedings of the 17th ACM Great Lakes symposium on VLSI
Fast convergence algorithm for decoding of low density parity check codes

WSEAS TRANSACTIONS on COMMUNICATIONS
Scalable communication architectures for massively parallel hardware multi-processors

Journal of Parallel and Distributed Computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

A DVB-S2 compliant codec is implemented in both 130nm-8M and 90nm-7M low-leakage CMOS technologies. The system includes encoders and decoders for both Low-Density Parity Check (LDPC) codes and serially concatenated BCH codes. All requirements of the DVB-S2 standard are supported including code rates between 1/4 and 9/10, block sizes of either 16,200 bits or 64,800 bits, and four digital modulation options. The 130nm core design occupies 49.6mm2 and operates at 200MHz, while the 90nm core design occupies 15.8mm2 and operates at 300MHz.