Quality-driven design in the system-on-a-chip era: why and how?
Journal of Systems Architecture: the EUROMICRO Journal - Modern methods and tools in digital system design
High-Level Synthesis of Nonprogrammable Hardware Accelerators
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Optimized Generation of Data-Path from C Codes for FPGAs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3)
Proceedings of the 42nd annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Massively LDPC Decoding on Multicore Architectures
IEEE Transactions on Parallel and Distributed Systems
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
GNLS: a hybrid on-chip communication architecture for SoC designs
International Journal of High Performance Systems Architecture
Communication on the Fly for Hierarchical Systems of Chip Multi-processors
PARELEC '11 Proceedings of the 2011 Sixth International Symposium on Parallel Computing in Electrical Engineering
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
FPGA Pipeline Synthesis Design Exploration Using Module Selection and Resource Sharing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-Level Synthesis for FPGAs: From Prototyping to Deployment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A multi-processor NoC-based architecture for real-time image/video enhancement
Journal of Real-Time Image Processing
Design of massively parallel hardware multi-processors for highly-demanding embedded applications
Microprocessors & Microsystems
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Modern complex embedded applications in multiple application fields impose stringent and continuously increasing functional and parametric demands. To adequately serve these applications, massively parallel multi-processor systems on a single chip (MPSoCs) are required. This paper is devoted to the design of scalable communication architectures of massively parallel hardware multi-processors for highly-demanding applications. We demonstrated that in the massively parallel hardware multi-processors the communication network influence on both the throughput and circuit area dominates the processors influence, while the traditionally used flat communication architectures do not scale well with the increase of parallelism. Therefore, we propose to design highly optimized application-specific partitioned hierarchical organizations of the communication architectures through exploiting the regularity and hierarchy of the actual information flows of a given application. We developed related communication architecture synthesis strategies and incorporated them into our quality-driven model-based multi-processor design methodology and related automated architecture exploration framework. Using this framework we performed a large series of architecture synthesis experiments. Some of the results of the experiments are presented in this paper. They demonstrate many features of the synthesized communication architectures and show that our method and related framework are able to efficiently synthesize well scalable communication architectures even for the high-end massively parallel multi-processors that have to satisfy extremely stringent computation demands.