Quality-driven design in the system-on-a-chip era: why and how?
Journal of Systems Architecture: the EUROMICRO Journal - Modern methods and tools in digital system design
High-Level Synthesis of Nonprogrammable Hardware Accelerators
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Optimized Generation of Data-Path from C Codes for FPGAs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-Level Synthesis: from Algorithm to Digital Circuit
High-Level Synthesis: from Algorithm to Digital Circuit
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Massively LDPC Decoding on Multicore Architectures
IEEE Transactions on Parallel and Distributed Systems
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
GNLS: a hybrid on-chip communication architecture for SoC designs
International Journal of High Performance Systems Architecture
Communication on the Fly for Hierarchical Systems of Chip Multi-processors
PARELEC '11 Proceedings of the 2011 Sixth International Symposium on Parallel Computing in Electrical Engineering
Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
FPGA Pipeline Synthesis Design Exploration Using Module Selection and Resource Sharing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-Level Synthesis for FPGAs: From Prototyping to Deployment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scalable communication architectures for massively parallel hardware multi-processors
Journal of Parallel and Distributed Computing
A multi-processor NoC-based architecture for real-time image/video enhancement
Journal of Real-Time Image Processing
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Many new embedded applications require complex computations to be performed to tight schedules, while at the same time demanding low energy consumption and low cost. For implementation of these highly-demanding applications, highly-optimized application-specific multi-processor system-on-a-chip (MPSoCs) are required involving hardware multi-processors to execute the critical computations. The multi-processor accelerator design for such applications has to adequately resolve several difficult issues. Since the processors' micro- and macro-architectures, as well as, the memory and communication architectures are strongly interrelated, they have to be designed in combination. Complex mutual tradeoffs have to be resolved among the processor micro- and macro-architecture, and the corresponding memory and communication architectures, as well as, among the performance, power consumption and area. Unfortunately, the design methods and tools published till now do not address most of the design issues of the massively parallel hardware multi-processor accelerators. This paper discusses our novel quality-driven model-based multi-processor accelerator design method that adequately addresses the architecture design issues of hardware multi-processors for the modern highly-demanding embedded applications. Using the design of LDPC decoders for the latest high-speed communication system standards as an example application, we performed an extensive experimental research of the multi-processor design issues, and of our method and its design space exploration (DSE) framework. The experiments clearly demonstrated the existence of various complex architecture tradeoffs that could only be resolved through an adequate quality-driven combined design space exploration of the processors' micro- and macro-architectures, and the corresponding memory and communication architectures, as delivered by our method.