Optimization of data-flow computations using canonical TED representation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level synthesis for the design of FPGA-based signal processing systems
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Construction of dual mode components for reconfiguration aware high-level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Optimizing data-flow graphs with min/max, adding and relational operations
Proceedings of the Conference on Design, Automation and Test in Europe
Optimizing data flow graphs to minimize hardware implementation
Proceedings of the Conference on Design, Automation and Test in Europe
An introduction to the SystemC synthesis subset standard
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Optimizing blocks in an SoC using symbolic code-statement reachability analysis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Design of complex image processing systems in ESL
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
High-level synthesis for designing multimode architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis
Journal of Signal Processing Systems
Abstraction in hardware system design
Communications of the ACM
Abstraction in Hardware System Design
Queue - Data
Enforcing architectural contracts in high-level synthesis
Proceedings of the 48th Design Automation Conference
Design of multi-mode application-specific cores based on high-level synthesis
Integration, the VLSI Journal
Efficient datapath merging for the overhead reduction of run-time reconfigurable systems
The Journal of Supercomputing
A modified merging approach for datapath configuration time reduction
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Towards a tighter integration of generated and custom-made hardware
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Aging analysis at gate and macro cell level
Proceedings of the International Conference on Computer-Aided Design
Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA
Proceedings of the 17th ACM SIGPLAN symposium on Principles and Practice of Parallel Programming
Divide and conquer high-level synthesis design space exploration
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
Architectural synthesis of flow-based microfluidic large-scale integration biochips
Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths
Integration, the VLSI Journal
Improving high level synthesis optimization opportunity through polyhedral transformations
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
FPGA programming for the masses
Communications of the ACM
A methodology for efficient use of OpenCL, ESL and FPGAs in multi-core architectures
Euro-Par'12 Proceedings of the 18th international conference on Parallel processing workshops
A heuristic scheduler for port-constrained floating-point pipelines
International Journal of Reconfigurable Computing
Multispeculative additive trees in high-level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient and scalable OpenMP-based system-level design
Proceedings of the Conference on Design, Automation and Test in Europe
Hardware design space exploration using HercuLeS HLS
Proceedings of the 17th Panhellenic Conference on Informatics
A direct method for optimal VLSI realization of deeply nested n-D loop problems
Microprocessors & Microsystems
SDC-based modulo scheduling for pipeline synthesis
Proceedings of the International Conference on Computer-Aided Design
Design of massively parallel hardware multi-processors for highly-demanding embedded applications
Microprocessors & Microsystems
Fast and standalone Design Space Exploration for High-Level Synthesis under resource constraints
Journal of Systems Architecture: the EUROMICRO Journal
Critical-path-aware high-level synthesis with distributed controller for fast timing closure
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. High-Level Synthesis: from Algorithm to Digital Circuit should be on each designers and CAD developers shelf, as well as on those of project managers who will soon embrace high level design and synthesis for all aspects of digital system design.