Power macromodeling for high level power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
A Fast Elitist Non-dominated Sorting Genetic Algorithm for Multi-objective Optimisation: NSGA-II
PPSN VI Proceedings of the 6th International Conference on Parallel Problem Solving from Nature
Efficient RTL Power Estimation for Large Designs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Hardware Implementation of ADABOOST ALGORITHM and Verification
AINAW '08 Proceedings of the 22nd International Conference on Advanced Information Networking and Applications - Workshops
High-Level Synthesis: from Algorithm to Digital Circuit
High-Level Synthesis: from Algorithm to Digital Circuit
Performance assessment of multiobjective optimizers: an analysis and review
IEEE Transactions on Evolutionary Computation
System-level design space exploration for three-dimensional (3D) SoCs
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications
Proceedings of the Conference on Design, Automation and Test in Europe
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This work presents the design of a complex image processing IP developed completely in C. We present the latest advanced in ESL-synthesis and demonstrate its main advantages over conventional RT-level flows. In particular we focus on the ability of behavioral synthesis to shorten the design cycle, perform functional verification and explore quickly the design space obtaining multiple dominating implementations with unique area vs. speed characteristics from an initial untimed behavioral description. A feature extraction process is presented in detailed showing how automatic design space exploration can lead to Pareto optimal (non-dominant) designs ranging from 524,648 gates to 584,868 gates and latencies of 38 to 69 state counts for the smallest and fastest design respectively taking approximately 6.3 hours.