Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Information theoretic measures of energy consumption at register transfer level
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Energy characterization based on clustering
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Register-transfer level estimation techniques for switching activity and power consumption
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Statistical sampling and regression analysis for RT-level power evaluation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
A power macromodeling technique based on power sensitivity
DAC '98 Proceedings of the 35th annual Design Automation Conference
Towards the capability of providing power-area-delay trade-off at the register transfer level
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
The petrol approach to high-level power estimation
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Cycle-accurate macro-models for RT-level power analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Computing Surveys (CSUR)
High-level power estimation with interconnect effects
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Characterization-free behavioral power modeling
Proceedings of the conference on Design, automation and test in Europe
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
A Methodology for High Level Power Estimation and Exploration
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
Clustered Table-Based Macromodels for RTL Power Estimation
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Accurate Power Macro-modeling Techniques for Complex RTL Circuits
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
High-level area and power estimation for VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analytical models for RTL power estimation of combinational and sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hardware Accelerated Power Estimation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Early Assessment of Leakage Power for System Level Design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Power emulation: a new paradigm for power estimation
Proceedings of the 42nd annual Design Automation Conference
Power estimation for cycle-accurate functional descriptions of hardware
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
PowerViP: Soc power estimation framework at transaction level
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Power signal processing: a new perspective for power analysis and optimization
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Testability analysis based on the identification of testable blocks with predefined properties
Microprocessors & Microsystems
Design of complex image processing systems in ESL
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Journal of Parallel and Distributed Computing
Delay constrained register transfer level dynamic power estimation
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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The adoption of register-transfer level (RTL) sign-off in ASIC designmethodologies, and the increasing scale of system-on-chip integration,are leading to unprecedented accuracy and efficiency demandson RT-level estimation tools. In this work, we focus onthe deployment of a simulation-based RTL power estimation toolin a commercial design flow, and describe several enhancementsthat improve its efficiency and scalability for large, industrial designs.We profile the computational effort involved in RTL powerestimation, and propose a suite of acceleration techniques, including(i) transformation of the enhanced RTL description (functionalmodel with annotations for power estimation) to be more simulator-friendly,(ii) computation vs. storage tradeoffs, and (iii) a novelvariation of statistical sampling, called partitioned sampling. Ourtechniques result in an optimized allocation of the overall computationaleffort for power estimation and minimize the computationaleffort involved in the evaluation of power models.Extensive experimental results in the context of a commercialdesign flow have yielded promising results (e.g., upto 31X reductionin power estimation time with negligible loss of accuracy) onindustrial designs of upto 1.25 million transistors. In addition toaccurate power estimation for an entire circuit, these accelerationtechniques result in superior accuracy of local power estimates forindividual components or small sub-circuits, compared to conventionalsampling or test-bench compaction techniques.