Towards the capability of providing power-area-delay trade-off at the register transfer level

Authors:
Chun-hong Chen;Chi-ying Tsui
Affiliations:
Department of Electrical and Electronic Engineering, The Hong Kong University of Science & Technology Clear Water Bay, Kowloon, Hong Kong;Department of Electrical and Electronic Engineering, The Hong Kong University of Science & Technology Clear Water Bay, Kowloon, Hong Kong
Venue:
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Year:
1998

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Abstract

This paper presents a new register-transfer level (RT-level) power estimation technique based on technology decomposition. Given the Boolean description of a circuit function, the power consumption of two typical circuit implementations, namely the minimum area implementation and the minimum delay implementation, are estimated, respectively. This provides a capability of obtaining a full power-delay-area trade-off curve at the RT level. Our method makes it possible to capture the structural and/or functional information of a circuit without going through actual gate-level implementation. Experimental results show that the accuracy is very reasonable.