ALU synthesis from HDL descriptions to optimized multi-level logic
EURO-DAC '92 Proceedings of the conference on European design automation
Information theoretic measures of energy consumption at register transfer level
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Towards a high-level power estimation capability
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Lower bounds on power dissipation for DSP algorithms
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
High-level power estimation and the area complexity of Boolean functions
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Behavioral Testability Insertion for Datapath/Controller Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Delay estimation VLSI circuits from a high-level view
DAC '98 Proceedings of the 35th annual Design Automation Conference
Towards the capability of providing power-area-delay trade-off at the register transfer level
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Power estimation of behavioral descriptions
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2002 international symposium on Low power electronics and design
REGISTER-TRANSFER LEVEL FAULT MODELING AND TEST EVALUATION TECHNIQUES FOR VLSI CIRCUITS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Entropies as Measures of Software Information
ICSM '01 Proceedings of the IEEE International Conference on Software Maintenance (ICSM'01)
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Cost-Driven Selection of Parity Trees
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
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The complexity of a Boolean function can be expressed in terms of computational work. We present experimental data in support of the entropy definition of computational work based upon the input-output description of a Boolean function. Our data show a linear relationship between the computational work and the average number of literals in a multi-level implementation. The investigation includes single-output and multi-output function with and without don't care states. The experiments, conducted on a large number of randomly generated functions, showed that the effect of don't cares is to reduce the computational work. For several finite state machine benchmarks, the computational work gave a good estimate of the size of the circuit. Finally, circuit delay is shown to have a non-linear relationship to the computational work.