An entropy measure for the complexity of multi-output Boolean functions
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
High-level power estimation and the area complexity of Boolean functions
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Accurate Entropy Calculation for Large Logic Circuits Based on Output Clustering
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
How an "Evolving" Fault Model Improves the Behavioral Test Generation
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Exact Computation of the Entropy of a Logic Circuit
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Towards a high-level power estimation capability [digital ICs]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Information theoretic measures for power analysis [logic design]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic state space decomposition for approximate FSM traversal based on circuit analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Theoretical bounds for switching activity analysis in finite-state machines
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
A Markov chain sequence generator for power macromodeling
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Power emulation: a new paradigm for power estimation
Proceedings of the 42nd annual Design Automation Conference
Power estimation for cycle-accurate functional descriptions of hardware
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
UVM-based verification methodology for RFID-enabled smart-sensor systems
Analog Integrated Circuits and Signal Processing
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This paper presents a methodology for power estimation of designs described at the behavioral-level as the interconnection of functional modules. The input/output behavior of each module is implicitly stored using BDDs, and the power consumed by the network is estimated using a novel and accurate entropy-based approach. As a demonstration example, we have used the proposed power estimation technique to evaluate and compare the effects of some architectural transformations applied to a reference design specification on the power dissipation of the corresponding implementations.