Algorithms for clustering data
Algorithms for clustering data
Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Information theoretic measures of energy consumption at register transfer level
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Analytical energy dissipation models for low-power caches
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Automatic characterization and modeling of power consumption in static RAMs
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
The petrol approach to high-level power estimation
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Cycle-accurate macro-models for RT-level power analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallel mixed-level power simulation based on spatio-temporal circuit partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Power estimation of behavioral descriptions
Proceedings of the conference on Design, automation and test in Europe
Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Power Aware Design Methodologies
Power Aware Design Methodologies
Efficient RTL Power Estimation for Large Designs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Hardware Accelerated Power Estimation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Power Analysis of System-Level On-Chip Communication Architectures
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
High-level area and power estimation for VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accelerating system-on-chip power analysis using hybrid power estimation
Proceedings of the 44th annual Design Automation Conference
Full-system chip multiprocessor power evaluations using FPGA-based emulation
Proceedings of the 13th international symposium on Low power electronics and design
An emulation-based real-time power profiling unit for embedded software
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Accelerating embedded software power profiling using run-time power emulation
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
POWER-MODES: POWer-EmulatoR- and MOdel-Based DEpendability and Security Evaluations
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Power monitoring for mixed-criticality on a many-core platform
ARCS'13 Proceedings of the 26th international conference on Architecture of Computing Systems
Estimation based power and supply voltage management for future RF-powered multi-core smart cards
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
An automatic energy consumption characterization of processors using ArchC
Journal of Systems Architecture: the EUROMICRO Journal
| Hi-index | 0.00 |
In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the observation that most power estimation tools typically perform the following sequence of operations: simulating the circuit to obtain value traces or statistics for the inputs of its constituent components, evaluating power models for each circuit component based on the input values seen during simulation, and aggregating the power consumption of individual components to compute the circuit's power consumption. We further recognize that the steps involved in power estimation (power model evaluation, aggregation) can themselves be thought of as synthesizable functions and implemented as hardware circuits. Thus, any given design can be enhanced by adding to it .power estimation hardware., and the resulting power model enhanced circuit can be mapped onto a hardware prototyping platform. While drastic speedups in power estimation (orders of magnitude) are possible using this approach, a significant challenge arises due to the increase in circuit size as a result of adding power estimation hardware. We propose a systematic methodology to reduce the size of the power model enhanced circuit through a suite of techniques, including power model reuse across different circuit components, regulating the granularity of components for power modeling, exploiting inter-component power correlations, resource sharing for power model computations, and the use of block memories for efficient storage within power models. We demonstrate the benefits of the proposed power emulation paradigm by applying it to register-transfer level (RTL) power estimation for industrial designs, resulting in speedups from around 10X to over 500X compared to state-of-the-art commercial power estimation tools.