A system-level methodology for fast multi-objective design space exploration
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Proceedings of the 2003 ACM symposium on Applied computing
Proceedings of the 2004 ACM symposium on Applied computing
Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Power analysis of system-level on-chip communication architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Safe integration of parameterized IP
Integration, the VLSI Journal - Special issue: IP and design reuse
Power emulation: a new paradigm for power estimation
Proceedings of the 42nd annual Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Integrating functional and power simulation in embedded systems design
Journal of Embedded Computing - Low-power Embedded Systems
Microprocessors & Microsystems
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Architectures with parameterizable cache and bus can support large tradeoffs between performance and power. We provide simulation data showing the large tradeoffs by such an architecture for several applications and demonstrating that the cache and bus should be configured simultaneously to find the optimal solutions. Furthermore, we describe analytical techniques for speeding up the cache/bus power and performance evaluation by several orders of magnitude over simulation, while maintaining sufficient accuracy with respect to simulation-based approaches.