Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Segmented bus design for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power estimation for architectural exploration of HW/SW communication on system-level buses
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A dictionary-based en/decoding scheme for low-power data buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
System-Level Power Analysis Methodology Applied to the AMBA AHB Bus
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
A global wiring paradigm for deep submicron design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Architectures and synthesis algorithms for power-efficient bus interfaces
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Architectural energy optimization by bus splitting
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Information Theoretic Capacity of Long On-chip Interconnects in the Presence of Crosstalk
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
NoCEE: energy macro-model extraction methodology for network on chip routers
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On-chip bus thermal analysis and optimization
Proceedings of the conference on Design, automation and test in Europe: Proceedings
System-level power-performance trade-offs in bus matrix communication architecture synthesis
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Proceedings of the conference on Design, automation and test in Europe
Slack allocation based co-synthesis and optimization of bus and memory architectures for MPSoCs
Proceedings of the conference on Design, automation and test in Europe
System-level PVT variation-aware power exploration of on-chip communication architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
Proceedings of the 46th Annual Design Automation Conference
System-level bus-based communication architecture exploration using a pseudoparallel algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Physical synthesis of bus matrix for high bandwidth low power on-chip communications
Proceedings of the 19th international symposium on Physical design
On-chip bus modeling for power and performance estimation
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power Modeling and Characterization of Computing Devices: A Survey
Foundations and Trends in Electronic Design Automation
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For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumption. Managing and optimizing this important component of SoC power requires a detailed understanding of the characteristics of its power consumption.Various power estimation and low-power design techniques have been proposed for the global interconnects that form part of SoC communication architectures (e.g., low-swing buses, bus encoding, etc). While effective, they only address a limited part of communication architecture power consumption. A state-of-the-art communication architecture, viewed in its entirety, is quite complex, comprising several components, such as bus interfaces, arbiters, bridges, decoders, and multiplexers, in addition to the global bus lines. Relatively little research has focused on analyzing and comparing the power consumed by different components of the communication architecture.In this work, we present a systematic evaluation and analysis of the power consumed by a state-of-the-art communication architecture (the AMBA on-chip bus), using a commercial design flow. We focus on developing a quantitative understanding of the relative contributions of different communication architecture components to its power consumption, and the factors on which they depend. We decompose the communication architecture power into power consumed by logic components (such as arbiters, decoders, bus bridges), global bus lines (that carry address, data, and control information), and bus interfaces. We also perform studies that analyze the impact of varying application traffic characteristics, and varying SoC complexity, on communication architecture power. Based on our analyses, we evaluate different techniques for reducing the power consumed by the on-chip communication architecture, and compare their effectiveness in achieving power savings at the system level. In addition to quantitatively reinforcing the view that on-chip communication is an important target for system-level power optimization, our work demonstrates (i) the importance of considering the communication architecture in its entirety, and (ii) the opportunities that exist for power reduction through careful communication architecture design.