Access pattern based local memory customization for low power embedded systems
Proceedings of the conference on Design, automation and test in Europe
Encodings for high-performance for energy-efficient signaling
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Low-energy for deep-submicron address buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Efficient power reduction techniques for time multiplexed address buses
Proceedings of the 15th international symposium on System Synthesis
Energy-reliability trade-off for NoCs
Networks on chip
Power efficient encoding techniques for off-chip data buses
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Adaptive low-power address encoding techniques using self-organizing lists
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Power analysis of system-level on-chip communication architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
PowerViP: Soc power estimation framework at transaction level
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Energy-efficient encoding techniques for off-chip data buses
ACM Transactions on Embedded Computing Systems (TECS)
System-level PVT variation-aware power exploration of on-chip communication architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Region-based routing: a mechanism to support efficient routing algorithms in NoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interframe bus encoding technique and architecture for MPEG-4 AVC/H.264 video compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Practical and theoretical considerations on low-power probability-codes for networks-on-chip
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Bus-switch coding for reducing power dissipation in off-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic memory access management for high-performance DSP applications using high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-Aware system-on-chip for 5 GHz wireless LANs
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Context-independent codes for off-chip interconnects
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
Partial bus-invert bus encoding schemes for low-power DSP systems considering inter-wire capacitance
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Automatic design of low-power encoders using reversible circuit synthesis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper we present algorithms for the synthesis of encoding and decoding interface logic that minimizes the average number of transitions on heavily-loaded global bus lines at no cost in communication throughput (i.e., one word is transmitted at each cycle). The distinguishing feature of our approach is that it does not rely on designer's intuition, but it automatically constructs low-transition activity codes and hardware implementation of encoders and decoders, given information on word-level statistics. We propose an accurate method that is applicable to low-width buses, as well as approximate methods that scale well with bus width. Furthermore, we introduce an adaptive architecture that automatically adjusts encoding to reduce transition activity on buses whose word-level statistics are not known a priori. Experimental results demonstrate that our approaches out-perform specialized low-power encoding schemes presented in the past