Dynamic base register caching: a technique for reducing address bus width
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Interface exploration for reduced power in core-based systems
Proceedings of the 11th international symposium on System synthesis
Working-zone encoding for reducing the energy in microprocessor address buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Frequent value locality and value-centric data cache design
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
FV encoding for low-power data I/O
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Low power address encoding using self-organizing lists
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
NetBench: a benchmarking suite for network processors
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
Power protocol: reducing power dissipation on off-chip data buses
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Creating a wider bus using caching techniques
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
An Adaptive Dictionary Encoding Scheme for SOC Data Buses
Proceedings of the conference on Design, automation and test in Europe
Frequent value encoding for low power data buses
ACM Transactions on Design Automation of Electronic Systems (TODAES)
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Architectures and synthesis algorithms for power-efficient bus interfaces
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Reducing the power consumption of computing devices has gained a lot of attention recently. Many research works have focused on reducing power consumption in the off-chip buses as they consume a significant amount of total power. Since the bus power consumption is proportional to the switching activity, reducing the bus switching is an effective way to reduce bus power. While numerous techniques exist for reducing bus power in address buses, only a handful of techniques have been proposed for data-bus power reduction, where frequent value encoding (FVE) is the best existing scheme to reduce the transition activity on the data buses. In this article, we propose improved frequent value data bus-encoding techniques aimed at reducing more switching activity and, hence, power consumption. We propose three new schemes and five new variations to exploit bit-wise temporal and spatial locality in the data-bus values. Our techniques just use one external control signal and capture bit-wise locality to efficiently encode data values. For all the embedded and SPEC applications we tested, the overall average switching reduction is 53% over unencoded data and 10% more than the conventional FVE scheme.