Computer organization (2nd ed.)
Computer organization (2nd ed.)
Microprocessor and peripheral handbook: volume 1—microprocessor
Microprocessor and peripheral handbook: volume 1—microprocessor
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Dynamic base register caching: a technique for reducing address bus width
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
An analysis of the information content of address reference streams
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
A guide to RISC microprocessors
A guide to RISC microprocessors
Modifying VM hardware to reduce address pin requirements
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Address compression through base register caching
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
ACM Computing Surveys (CSUR)
IEEE Micro
Using cache memory to reduce processor-memory traffic
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Information content of CPU memory referencing behavior
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
AFIPS '72 (Spring) Proceedings of the May 16-18, 1972, spring joint computer conference
Memory bandwidth limitations of future microprocessors
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
The processor-memory bottleneck: problems and solutions
Crossroads - Computer architecture
Effective algorithms for cache-level compression
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Limited Bandwidth to Affect Processor Design
IEEE Micro
The performance advantage of applying compression to the memory system
Proceedings of the 2002 workshop on Memory system performance
Power protocol: reducing power dissipation on off-chip data buses
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Adaptive Cache Compression for High-Performance Processors
Proceedings of the 31st annual international symposium on Computer architecture
A Robust Main-Memory Compression Scheme
Proceedings of the 32nd annual international symposium on Computer Architecture
A tunable bus encoder for off-chip data buses
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Optimizing bus energy consumption of on-chip multiprocessors using frequent values
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Parallel, distributed and network-based processing
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Power-efficient and scalable load/store queue design via address compression
Proceedings of the 2008 ACM symposium on Applied computing
Energy-efficient encoding techniques for off-chip data buses
ACM Transactions on Embedded Computing Systems (TECS)
Adaptive data compression for high-performance low-power on-chip networks
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Notary: Hardware techniques to enhance signatures
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Efficient lookahead routing and header compression for multicasting in networks-on-chip
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Dynamic dictionary-based data compression for level-1 caches
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
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The effective bandwidth of a bus and external communication ports can be increased by using a variant of data compression techniques that compacts words instead of data streams. The compaction is performed by caching the high order bits into a table and sending the index into the table along with the low order bits. A coherent table at the receiving end expands the word into it original form. Compaction/expansion units can be placed between processor and memory, between processor and local bus, and between devices that access the system bus. Simulations have shown that over 90% of all informative transferred can be sent in a single cycle when using a 32 bit processor connected by a 16 bit wide bus to a 32 bit memory module. This is for all forms of data, address, data, and instructions, and when a cache-based processor is used.