Sequentiality and prefetching in database systems
ACM Transactions on Database Systems (TODS)
Characterizing the Storage Process and Its Effect on the Update of Main Memory by Write Through
Journal of the ACM (JACM)
Cache Performance in the VAX-11/780
ACM Transactions on Computer Systems (TOCS)
A simple linear model of demand paging performance
Communications of the ACM
The working set model for program behavior
Communications of the ACM
Operating Systems Theory
Performance Evaluation of a Cache Memory for a Mini-computer
Proceedings of the Third International Symposium on Modelling and Performance Evaluation of Computer Systems: Performance of Computer Systems
Bibliography on paging and related topics
ACM SIGOPS Operating Systems Review
Effects of cache coherency in multiprocessors
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
Register allocation for free: The C machine stack cache
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
Lockup-free instruction fetch/prefetch cache organization
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Analysis of multiprocessor cache organizations with alternative main memory update policies
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
A processor for a high-performance personal computer
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
The architecture of the SPERRY UNIVAC 1100 series systems
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Cache memories for PDP-11 family computers
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Performance of cache-based multiprocessors
SIGMETRICS '81 Proceedings of the 1981 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Performance evaluation and prediction of storage hierarchies
PERFORMANCE '80 Proceedings of the 1980 international symposium on Computer performance modelling, measurement and evaluation
SOSP '77 Proceedings of the sixth ACM symposium on Operating systems principles
Performance of the GE-645 associative memory while Multics is in operation
Proceedings of the SIGOPS workshop on System performance evaluation
A few examples of how to use a symmetrical multi-micro-processor
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
An instruction timing model of CPU performance
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
High-speed buffering for variable length operands
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
AN EXPERIMENTAL ANALYSIS OF PROGRAM REFERENCE PATTERNS IN THE MULTICS VIRTUAL MEMORY
AN EXPERIMENTAL ANALYSIS OF PROGRAM REFERENCE PATTERNS IN THE MULTICS VIRTUAL MEMORY
S-1 architecture manual
Sequential prefetch strategies for instructions and data
Sequential prefetch strategies for instructions and data
Analysis of Branch Prediction Strategies and Branch Target Buffer
Analysis of Branch Prediction Strategies and Branch Target Buffer
Hardware-controlled memory hierarchies and their performance.
Hardware-controlled memory hierarchies and their performance.
The design and management of predictive caches
The design and management of predictive caches
The Efficient Use of Buffer Storage
ACM '77 Proceedings of the 1977 annual conference
Disk cache—miss ratio analysis and design considerations
ACM Transactions on Computer Systems (TOCS)
An Empirical Study of Task Switching Locality in MVS
IEEE Transactions on Computers
Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
Memory coherence in shared virtual memory systems
PODC '86 Proceedings of the fifth annual ACM symposium on Principles of distributed computing
Comments on "A Massive Memory Machine"
IEEE Transactions on Computers
ATUM: a new technique for capturing address traces using microcode
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
An in-cache address translation mechanism
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Software-controlled caches in the VMP multiprocessor
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
On the use of registers vs. cache to minimize memory traffic
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
A class of compatible cache consistency protocols and their support by the IEEE futurebus
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Multiprocessor cache synchronization: issues, innovations, evolution
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Memory access buffering in multiprocessors
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
A perspective on the 801/Reduced Instruction Set Computer
IBM Systems Journal
An implementation independent approach to cache memories
ACM SIGARCH Computer Architecture News
On cacheability of lock-variables in tightly coupled multiprocessor systems
ACM SIGARCH Computer Architecture News
A model for hierarchical memory
STOC '87 Proceedings of the nineteenth annual ACM symposium on Theory of computing
Line (block) size choice for CPU cache memories
IEEE Transactions on Computers
SIGMETRICS '87 Proceedings of the 1987 ACM SIGMETRICS conference on Measurement and modeling of computer systems
A unified resource management and execution control mechanism for data flow machines
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
An architectural perspective on a memory access controller
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Organization and analysis of a gracefully-degrading interleaved memory system
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Correct memory operation of cache-based multiprocessors
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Multiprocessor cache design considerations
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Architectural tradeoffs in the design of MIPS-X
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Characterization of branch and data dependencies on programs for evaluating pipeline performance
IEEE Transactions on Computers
ACM Transactions on Computer Systems (TOCS)
The effect of instruction set complexity on program size and memory performance
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Coherency for multiprocessor virtual address caches
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Firefly: a multiprocessor workstation
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Checkpoint repair for high-performance out-of-order execution machines
IEEE Transactions on Computers
SIGIR '87 Proceedings of the 10th annual international ACM SIGIR conference on Research and development in information retrieval
801 storage: architecture and programming
ACM Transactions on Computer Systems (TOCS)
Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses
IEEE Transactions on Computers
Cache Operations by MRU Change
IEEE Transactions on Computers
The Balance Multiprocessor System
IEEE Micro
Cache performance of operating system and multiprogramming workloads
ACM Transactions on Computer Systems (TOCS)
Structuring an instruction cache
ACM SIGARCH Computer Architecture News
Firefly: A Multiprocessor Workstation
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
A VLIW architecture for a trace Scheduling Compiler
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems
IEEE Transactions on Computers
An analysis of Memnet—an experiment in high-speed shared-memory local networking
SIGCOMM '88 Symposium proceedings on Communications architectures and protocols
Analysis of memory referencing behavior for design of local memories
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
A simulation study of two-level caches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Multiprocessor cache analysis using ATUM
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Cache performance of vector processors
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
An evaluation of directory schemes for cache coherence
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Design and performance of special purpose hardware for time warp
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
The VMP multiprocessor: initial experience, refinements, and performance evaluation
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Data buffer performance for sequential Prolog architectures
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
A Case for Direct-Mapped Caches
Computer
Dynamic RAM for on-chip instruction caches
ACM SIGARCH Computer Architecture News - Special Issue: Architectural Support for Operating Systems
A two-tier memory architecture for high-performance multiprocessor systems
ICS '88 Proceedings of the 2nd international conference on Supercomputing
Distributed shared memory in a loosely coupled distributed system
SIGCOMM '87 Proceedings of the ACM workshop on Frontiers in computer communications technology
Efficient (stack) algorithms for analysis of write-back and sector memories
ACM Transactions on Computer Systems (TOCS)
Characterizing the synchronization behavior of parallel programs
PPEALS '88 Proceedings of the ACM/SIGPLAN conference on Parallel programming: experience with applications, languages and systems
Efficient and realistic simulation of disk cache performance
ANSS '88 Proceedings of the 21st annual symposium on Simulation
Tokenless static data flow using associative templates
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
The design of a lockup-free cache for high-performance multiprocessors
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Concurrent I/O system for the hypercube multiprocessor
C3P Proceedings of the third conference on Hypercube concurrent computers and applications - Volume 2
The Clipper processor: instruction set architecture and implementation
Communications of the ACM
Cache Memory Organization to Enhance the Yield of High Performance VLSI Processors
IEEE Transactions on Computers
ACM Transactions on Computer Systems (TOCS)
Improving Quicksort Performance with a Codeword Data Structure
IEEE Transactions on Software Engineering
A unified vector/scalar floating-point architecture
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Program optimization for instruction caches
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Evaluating the performance of software cache coherence
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
The Stack Growth Function: Cache Line Reference Models
IEEE Transactions on Computers
Multiplier/Shifter Design Tradeoffs in a 32-bit Microprocessor
IEEE Transactions on Computers
IEEE Transactions on Computers
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
Unified management of registers and cache using liveness and cache bypass
PLDI '89 Proceedings of the ACM SIGPLAN 1989 Conference on Programming language design and implementation
Multi-level shared caching techniques for scalability in VMP-M/C
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Design and performance of a coherent cache for parallel logic programming architectures
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Characteristics of performance-optimal multi-level cache hierarchies
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Supporting reference and dirty bits in SPUR's virtual address cache
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Inexpensive implementations of set-associativity
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Organization and performance of a two-level virtual-real cache hierarchy
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Improving performance of small on-chip instruction caches
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Achieving high instruction cache performance with an optimizing compiler
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
The impact of code density on instruction cache performance
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Performance measurements on a commercial multiprocessor running parallel code
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Memory coherence in shared virtual memory systems
ACM Transactions on Computer Systems (TOCS)
Evaluating Associativity in CPU Caches
IEEE Transactions on Computers
Design and Analysis of a Gracefully Degrading Interleaved Memory System
IEEE Transactions on Computers
Cache considerations for multiprocessor programmers
Communications of the ACM
Memory Access Dependencies in Shared-Memory Multiprocessors
IEEE Transactions on Software Engineering
IBM Systems Journal
Data caching issues in an information retrieval system
ACM Transactions on Database Systems (TODS)
Quick and easy cache performance analysis
ACM SIGARCH Computer Architecture News
Cache performance of the integer SPEC benchmarks on a RISC
ACM SIGARCH Computer Architecture News
Analysis of multithreaded architectures for parallel computing
SPAA '90 Proceedings of the second annual ACM symposium on Parallel algorithms and architectures
Distributed file systems: concepts and examples
ACM Computing Surveys (CSUR)
Techniques for efficient inline tracing on a shared-memory multiprocessor
SIGMETRICS '90 Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Data cache management using frequency-based replacement
SIGMETRICS '90 Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems
An approximate analysis of the LRU and FIFO buffer replacement schemes
SIGMETRICS '90 Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems
The effects of processor architecture on instruction memory traffic
ACM Transactions on Computer Systems (TOCS)
The Evolution of Instruction Sequencing
Computer - Special issue on instruction sequencing
Computer - Special issue on experimental research in computer architecture
High-bandwidth data memory systems for superscalar processors
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
The effect of context switches on cache performance
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
A model for estimating trace-sample miss ratios
SIGMETRICS '91 Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems
The impact of memory organization on the performance of matrix multiplication
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Improving instruction cache behavior by reducing cache pollution
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Data cache performance of supercomputer applications
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Performance Measurement and Modeling to Evaluate Various Effects on a Shared memory Multiprocessor
IEEE Transactions on Software Engineering
Branch history table prediction of moving target branches due to subroutine returns
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
An architecture for software-controlled data prefetching
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Data prefetching in multiprocessor vector cache memories
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Evaluation of memory system extensions
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Classification and performance evaluation of instruction buffering techniques
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
On the validity of trace-driven simulation for multiprocessors
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
A low-cost usage-based replacement algorithm for cache memories
ACM SIGARCH Computer Architecture News
On reconfigurable on-chip data caches
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
An effective on-chip preloading scheme to reduce data access penalty
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Using Lookahead to reduce memory bank contention for decoupled operand references
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Cache behavior of combinator graph reduction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Subprogram Inlining: A Study of its Effects on Program Execution Time
IEEE Transactions on Software Engineering
A class of replacement policies for medium and high-associativity structures
ACM SIGARCH Computer Architecture News
Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment
IEEE Transactions on Computers
Synchronization mechanisms for distributed event-driven computation
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Fast instruction cache performance evaluation using compile-time analysis
SIGMETRICS '92/PERFORMANCE '92 Proceedings of the 1992 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
Computing with faulty shared memory
PODC '92 Proceedings of the eleventh annual ACM symposium on Principles of distributed computing
Synthetic Traces for Trace-Driven Simulation of Cache Memories
IEEE Transactions on Computers
Design and Evaluation of the Rollback Chip: Special Purpose Hardware for Time Warp
IEEE Transactions on Computers
Page placement algorithms for large real-indexed caches
ACM Transactions on Computer Systems (TOCS)
Performance evaluation of a decoded instruction cache for variable instruction-length computers
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
A simulation based study of TLB performance
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Cache replacement with dynamic exclusion
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Memory latency effects in decoupled architectures with a single data memory module
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
A novel cache design for vector processing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Tradeoffs in supporting two page sizes
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Improving Disk Cache Hit-Ratios Through Cache Partitioning
IEEE Transactions on Computers
Cache Memories for Data Flow Machines
IEEE Transactions on Computers
Design choices for the TOP-1 multiprocessor workstation
IBM Journal of Research and Development
ACM SIGMETRICS Performance Evaluation Review
The effects of virtually addressed caches on virtual memory design and performance
ACM SIGOPS Operating Systems Review
Prefetch unit for vector operations on scalar computers
ACM SIGARCH Computer Architecture News
Avoiding unconditional jumps by code replication
PLDI '92 Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation
Optimally profiling and tracing programs
POPL '92 Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Software support for speculative loads
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Architecture support for single address space operating systems
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Stride directed prefetching in scalar processors
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
The effect of page allocation on caches
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Optimal Partitioning of Cache Memory
IEEE Transactions on Computers
Persistent Caching: An Implementation Technique for Complex Objects with Object Identity
IEEE Transactions on Software Engineering
Prefetching in supercomputer instruction caches
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Sparse matrix computations: implications for cache designs
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Pseudo vector processor based on register-windowed superscalar pipeline
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
An effective write policy for software coherence schemes
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
ACM Transactions on Programming Languages and Systems (TOPLAS)
A process-dependent partitioning strategy for cache memories
ACM SIGARCH Computer Architecture News
Evaluating performance of prefetching second level caches
ACM SIGMETRICS Performance Evaluation Review
Cache coherence in large-scale shared-memory multiprocessors: issues and comparisons
ACM Computing Surveys (CSUR)
A case for two-way skewed-associative caches
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Column-associative caches: a technique for reducing the miss rate of direct-mapped caches
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Cache write policies and performance
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
A scalar architecture for pseudo vector processing based on slide-windowed registers
ICS '93 Proceedings of the 7th international conference on Supercomputing
Introducing a New Cache Design into Vector Computers
IEEE Transactions on Computers
Evaluating models of memory allocation
ACM Transactions on Modeling and Computer Simulation (TOMACS)
SCISM: a scalable compound instruction set machine
IBM Journal of Research and Development
The effectiveness of caches for vector processors
ICS '94 Proceedings of the 8th international conference on Supercomputing
Using virtual lines to enhance locality exploitation
ICS '94 Proceedings of the 8th international conference on Supercomputing
Linear logic and permutation stacks—the Forth shall be first
ACM SIGARCH Computer Architecture News - Special issue: panel sessions of the 1991 workshop on multithreaded computers
SIGMETRICS '94 Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Optimally profiling and tracing programs
ACM Transactions on Programming Languages and Systems (TOPLAS)
Request Combining in Multiprocessors with Arbitrary Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
Partition selection policies in object database garbage collection
SIGMOD '94 Proceedings of the 1994 ACM SIGMOD international conference on Management of data
Evaluating stream buffers as a secondary cache replacement
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Exploring the design space for a shared-cache multiprocessor
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
A performance study of software and hardware data prefetching schemes
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
A study of single-chip processor/cache organizations for large numbers of transistors
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
A unified architectural tradeoff methodology
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Expected I-cache miss rates via the gap model
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Cache designs with partial address matching
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Trap-driven simulation with Tapeworm II
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Avoiding conflict misses dynamically in large direct-mapped caches
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Surpassing the TLB performance of superpages with less operating system support
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Set-associative cache simulation using generalized binomial trees
ACM Transactions on Computer Systems (TOCS)
Avoiding conditional branches by code replication
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Tile size selection using cache organization and data layout
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Performance effects of architectural complexity in the Intel 432
ACM Transactions on Computer Systems (TOCS)
Performance of the VAX-11/780 translation buffer: simulation and measurement
ACM Transactions on Computer Systems (TOCS)
The unconventional replacement algorithms
ACM SIGARCH Computer Architecture News
Performance of cache coherence in stackable filing
SOSP '95 Proceedings of the fifteenth ACM symposium on Operating systems principles
Energy optimization of multi-level processor cache architectures
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Design of cache memories for multi-threaded dataflow architecture
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Instruction fetching: coping with code bloat
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Instruction cache fetch policies for speculative execution
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Hardware implementation issues of data prefetching
ICS '95 Proceedings of the 9th international conference on Supercomputing
SPAID: software prefetching in pointer- and call-intensive environments
Proceedings of the 28th annual international symposium on Microarchitecture
Computing with faulty shared objects
Journal of the ACM (JACM)
Matrix Partitioning on a Virtual Shared Memory Parallel Machine
IEEE Transactions on Parallel and Distributed Systems
Memory bandwidth limitations of future microprocessors
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Instruction prefetching of systems codes with layout optimized for reduced cache misses
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
A quantitative analysis of loop nest locality
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Value locality and load value prediction
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Improving cache performance with balanced tag and data paths
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
The Cache Assignment Problem and Its Application to Database Buffer Management
IEEE Transactions on Software Engineering
Strategic directions in computer architecture
ACM Computing Surveys (CSUR) - Special ACM 50th-anniversary issue: strategic directions in computing research
ACM SIGARCH Computer Architecture News
The impact of a zero-scan Internet checksumming mechanism
ACM SIGCOMM Computer Communication Review
Architecture Technique Trade-Offs Using Mean Memory Delay Time
IEEE Transactions on Computers
An Analytical Model for Designing Memory Hierarchies
IEEE Transactions on Computers
Compiler synthesized dynamic branch prediction
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Wrong-path instruction prefetching
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Design decisions influencing the UltraSPARC's instruction fetch architecture
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Instruction fetch mechanisms for VLIW architectures with compressed encodings
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Locality As a Visualization Tool
IEEE Transactions on Computers
Trap-driven memory simulation with Tapeworm II
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Trace-driven memory simulation: a survey
ACM Computing Surveys (CSUR)
Two-ported cache alternatives for superscalar processors
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
The selection of optimal cache lines for microprocessor-based controllers
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
A memory management unit and cache controller for the MARS system
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Analytical energy dissipation models for low-power caches
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Improving data cache performance by pre-executing instructions under a cache miss
ICS '97 Proceedings of the 11th international conference on Supercomputing
Eliminating cache conflict misses through XOR-based placement functions
ICS '97 Proceedings of the 11th international conference on Supercomputing
Data prefetching on the HP PA-8000
Proceedings of the 24th annual international symposium on Computer architecture
Run-time adaptive cache hierarchy management via reference analysis
Proceedings of the 24th annual international symposium on Computer architecture
Remembrance of things past: locality and memory in BDDs
DAC '97 Proceedings of the 34th annual Design Automation Conference
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Run-time spatial locality detection and optimization
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The design and performance of a conflict-avoiding cache
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Prediction caches for superscalar processors
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Performance analysis on a CC-NUMA prototype
IBM Journal of Research and Development - Special issue: performance analysis and its impact on design
Profetching and memory system behavior of the SPEC95 benchmark suite
IBM Journal of Research and Development - Special issue: performance analysis and its impact on design
NStrace: a bus-driven instruction trace tool for PowerPC microprocessors
IBM Journal of Research and Development - Special issue: performance analysis and its impact on design
Load execution latency reduction
ICS '98 Proceedings of the 12th international conference on Supercomputing
Characterization and improvement of load/store cache-based prefetching
ICS '98 Proceedings of the 12th international conference on Supercomputing
Hardware-driven prefetching for pointer data references
ICS '98 Proceedings of the 12th international conference on Supercomputing
Exploiting spatial locality in data caches using spatial footprints
Proceedings of the 25th annual international symposium on Computer architecture
Low load latency through sum-addressed memory (SAM)
Proceedings of the 25th annual international symposium on Computer architecture
A Performance Study of Instruction Cache Prefetching Methods
IEEE Transactions on Computers
CPU Cache Prefetching: Timing Evaluation of Hardware Implementations
IEEE Transactions on Computers
Combining Trace Sampling with Single Pass Methods for Efficient Cache Simulation
IEEE Transactions on Computers
25 years of the international symposia on Computer architecture (selected papers)
Using cache memory to reduce processor-memory traffic
25 years of the international symposia on Computer architecture (selected papers)
A low-overhead coherence solution for multiprocessors with private cache memories
25 years of the international symposia on Computer architecture (selected papers)
An evaluation of directory schemes for cache coherence
25 years of the international symposia on Computer architecture (selected papers)
25 years of the international symposia on Computer architecture (selected papers)
Using generational garbage collection to implement cache-conscious data placement
Proceedings of the 1st international symposium on Memory management
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Capturing dynamic memory reference behavior with adaptive cache topology
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Functional Implementation Techniques for CPU Cache Memories
IEEE Transactions on Computers - Special issue on cache memory and related problems
Randomized Cache Placement for Eliminating Conflicts
IEEE Transactions on Computers - Special issue on cache memory and related problems
Cache conscious programming in undergraduate computer science
SIGCSE '99 The proceedings of the thirtieth SIGCSE technical symposium on Computer science education
Cache-conscious structure layout
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation
The pool of subsectors cache design
ICS '99 Proceedings of the 13th international conference on Supercomputing
A locality sensitive multi-module cache with explicit management
ICS '99 Proceedings of the 13th international conference on Supercomputing
Optimal replacements in caches with two miss costs
Proceedings of the eleventh annual ACM symposium on Parallel algorithms and architectures
An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors
International Journal of Parallel Programming
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Competitive algorithms for multilevel caching and relaxed list update
Proceedings of the ninth annual ACM-SIAM symposium on Discrete algorithms
An Easy-to-Use Approach for Practical Bus-Based System Design
IEEE Transactions on Computers
SIGMETRICS '86/PERFORMANCE '86 Proceedings of the 1986 ACM SIGMETRICS joint international conference on Computer performance modelling, measurement and evaluation
SIGMETRICS '86/PERFORMANCE '86 Proceedings of the 1986 ACM SIGMETRICS joint international conference on Computer performance modelling, measurement and evaluation
Fundamentals of parallel logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Influence of the stride on the cache utilization in the IBM 3090 VF
ICS '89 Proceedings of the 3rd international conference on Supercomputing
Fetch directed instruction prefetching
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Hardware identification of cache conflict misses
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Access region locality for high-bandwidth processor memory system design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Frame caching in menu-driven Videotex systems
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
An empirical evaluation of two memory-efficient directory methods
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
The performance impact of block sizes and fetch strategies
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Generation and analysis of very long address traces
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
The TLB slice—a low-cost high-speed address translation mechanism
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Issues related to MIMD shared-memory computers: the NYU ultracomputer approach
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
An architecture for high volume transaction processing
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
CSC '91 Proceedings of the 19th annual conference on Computer Science
Implementing a cache consistency protocol
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Parallel trace-driven cache simulation by time partitioning
WSC' 90 Proceedings of the 22nd conference on Winter simulation
Quantifying loop nest locality using SPEC'95 and the perfect benchmarks
ACM Transactions on Computer Systems (TOCS)
Procedure placement using temporal-ordering information
ACM Transactions on Programming Languages and Systems (TOPLAS)
IEEE Transactions on Computers
Push vs. pull: data movement for linked data structures
Proceedings of the 14th international conference on Supercomputing
Boosting superpage utilization with the shadow memory and the partial-subblock TLB
Proceedings of the 14th international conference on Supercomputing
Making B+- trees cache conscious in main memory
SIGMOD '00 Proceedings of the 2000 ACM SIGMOD international conference on Management of data
Efficient and Precise Cache Behavior Prediction for Real-TimeSystems
Real-Time Systems
Symbolic Cache Analysis for Real-Time Systems
Real-Time Systems - Special issue on worst-case execution-time analysis
The Journal of Supercomputing
Cache Performance in the VAX-11/780
ACM Transactions on Computer Systems (TOCS)
Transient behavior of cache memories
ACM Transactions on Computer Systems (TOCS)
The software lookaside buffler reduces search overhead with linked lists
Communications of the ACM
ACM Computing Surveys (CSUR)
Memory Hierarchy Considerations for Cost-Effective Cluster Computing
IEEE Transactions on Computers
Architectural and compiler support for effective instruction prefetching: a cooperative approach
ACM Transactions on Computer Systems (TOCS)
Source-to-Source Instrumentation for the Optimization of an Automatic Reading System
The Journal of Supercomputing
Optimizations Enabled by a Decoupled Front-End Architecture
IEEE Transactions on Computers
Exploring multimedia applications locality to improve cache performance
MULTIMEDIA '00 Proceedings of the eighth ACM international conference on Multimedia
Cache performance for multimedia applications
ICS '01 Proceedings of the 15th international conference on Supercomputing
A novel renaming mechanism that boosts software prefetching
ICS '01 Proceedings of the 15th international conference on Supercomputing
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Dead-block prediction & dead-block correlating prefetchers
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Establishing a tight bound on task interference in embedded system instruction caches
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Runtime identification of cache conflict misses: The adaptive miss buffer
ACM Transactions on Computer Systems (TOCS)
A process cache memory for tightly coupled multiprocessor systems
ACM-SE 30 Proceedings of the 30th annual Southeast regional conference
IEEE Transactions on Computers
Designing a Modern Memory Hierarchy with Hardware Prefetching
IEEE Transactions on Computers
Lookahead Scheduling Requests for Multisize Page Caching
IEEE Transactions on Computers
Facilitating level three cache studies using set sampling
Proceedings of the 32nd conference on Winter simulation
Workload characterization of emerging computer applications
Execution history guided instruction prefetching
ICS '02 Proceedings of the 16th international conference on Supercomputing
Timekeeping in the memory system: predicting and optimizing memory behavior
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Cache performance in vector supercomputers
Proceedings of the 1994 ACM/IEEE conference on Supercomputing
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Journal of Computer Science and Technology
Load Balancing for Parallel Query Execution on NUMA Multiprocessors
Distributed and Parallel Databases
IEEE Internet Computing
Optimizing a Superscalar Machine to Run Vector Code
IEEE Parallel & Distributed Technology: Systems & Technology
Splitting the Data Cache: A Survey
IEEE Concurrency
Exploiting Coherence for Multiprocessor Ray Tracing
IEEE Computer Graphics and Applications
Microprocessor Memory Management Units
IEEE Micro
Motorola's 88000 Family Architecture
IEEE Micro
The Gmicro/300 32-Bit Microprocessor
IEEE Micro
IEEE Micro
The ChARM Tool for Tuning Embedded Systems
IEEE Micro
Modeling Live and Dead Lines in Cache Memory Systems
IEEE Transactions on Computers
Performance Implications of Tolerating Cache Faults
IEEE Transactions on Computers
IEEE Transactions on Computers
Designing High-Performance Processors Using Real Address Prediction
IEEE Transactions on Computers
The Effect of Code Expanding Optimizations on Instruction Cache Design
IEEE Transactions on Computers
A Quantitative Evaluation of Cache Types for High-Performance Computer Systems
IEEE Transactions on Computers
A Comparison of Trace-Sampling Techniques for Multi-Megabyte Caches
IEEE Transactions on Computers
False Sharing and Spatial Locality in Multiprocessor Caches
IEEE Transactions on Computers
IEEE Transactions on Computers
Memory Latency Effects in Decoupled Architectures
IEEE Transactions on Computers
Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length Computers
IEEE Transactions on Computers
Effective Hardware-Based Data Prefetching for High-Performance Processors
IEEE Transactions on Computers
Measuring Cache and TLB Performance and Their Effect on Benchmark Runtimes
IEEE Transactions on Computers
Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches
IEEE Transactions on Computers
A Highly Effective Partition Selection Policy for Object Database Garbage Collection
IEEE Transactions on Knowledge and Data Engineering
Prefetching in File Systems for MIMD Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Accuracy of Memory Reference Traces of Parallel Computations in Trace-Drive Simulation
IEEE Transactions on Parallel and Distributed Systems
An Analysis of Cache Performance for a Hypercube Multicomputer
IEEE Transactions on Parallel and Distributed Systems
Performance Measurement Intrusion and Perturbation Analysis
IEEE Transactions on Parallel and Distributed Systems
Performance Tradeoffs in Multithreaded Processors
IEEE Transactions on Parallel and Distributed Systems
The Impact of Parallel Loop Scheduling Strategies on Prefetching in a Shared Memory Multiprocessor
IEEE Transactions on Parallel and Distributed Systems
Sequential Hardware Prefetching in Shared-Memory Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems
IEEE Transactions on Parallel and Distributed Systems
Stack Evaluation of Arbitrary Set-Associative Multiprocessor Caches
IEEE Transactions on Parallel and Distributed Systems
Increasing hardware data prefetching performance using the second-level cache
Journal of Systems Architecture: the EUROMICRO Journal
Multiple Prefetch Adaptive Disk Caching
IEEE Transactions on Knowledge and Data Engineering
Stride-directed Prefetching for Secondary Caches
ICPP '97 Proceedings of the international Conference on Parallel Processing
An adaptive sequential prefetching scheme in shared-memory multiprocessors
ICPP '97 Proceedings of the international Conference on Parallel Processing
A Hardware Scheme for Data Prefetching
HPCN Europe 2000 Proceedings of the 8th International Conference on High-Performance Computing and Networking
A PIM-based Multiprocessor System
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Implementations of Real-time Data Intensive Applications on PIM-based Multiprocessor Systems
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Cache Conscious Indexing for Decision-Support in Main Memory
VLDB '99 Proceedings of the 25th International Conference on Very Large Data Bases
A Comparison of Locality-Based and Recency-Based Replacement Policies
ISHPC '00 Proceedings of the Third International Symposium on High Performance Computing
Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
The Multi-Queue Replacement Algorithm for Second Level Buffer Caches
Proceedings of the General Track: 2002 USENIX Annual Technical Conference
Trace-Driven Memory Simulation: A Survey
Performance Evaluation: Origins and Directions
Cache Conscious Algorithms for Relational Query Processing
VLDB '94 Proceedings of the 20th International Conference on Very Large Data Bases
Proceedings of the 2002 ACM/IEEE conference on Supercomputing
Improving cache hit ratio by extended referencing cache lines
Journal of Computing Sciences in Colleges
Dynamic memory instruction bypassing
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
A Measurement Study of Memory Transaction Characteristics on a PowerPC Based Macintosh
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Improving Performance for Software MPEG Players
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Architecture of a VLSI instruction cache for a RISC
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Using cache memory to reduce processor-memory traffic
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A study of instruction cache organizations and replacement policies
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Experimental evaluation of on-chip microprocessor cache memories
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
The use of static column ram as a memory hierarchy
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
A low-overhead coherence solution for multiprocessors with private cache memories
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
An economical solution to the cache coherence problem
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Cache hit ratios with geometric task switch intervals
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
U-cache: a cost-effective solution to synonym problem
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Creating a wider bus using caching techniques
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
The impact of shared-cache clustering in small-scale shared-memory multiprocessors
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Distributed Prefetch-buffer/Cache Design for High Performance Memory Systems
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Cost-Sensitive Cache Replacement Algorithms
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Evaluation of cache consistency algorithm performance
MASCOTS '96 Proceedings of the 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
Memory Hierarchy Design for Jetpipeline: To Execute Scalar and Vector Instructions in Parallel
PAS '97 Proceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis
Prefetching by Self-Contained Variables - a Generalization from Array to Recursive Data Structures
PAS '97 Proceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis
Energy-Efficiency of VLSI Caches: A Comparative Study
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Determining WWW User's Next Access and Its Application to Pre-fetching
ISCC '97 Proceedings of the 2nd IEEE Symposium on Computers and Communications (ISCC '97)
DRAM-Page Based Prediction and Prefetching
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A Study of Channeled DRAM Memory Architectures
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A Selective Temporal and Aggressive Spatial Cache System Based on Time Interval
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Caches versus object allocation
IWOOOS '96 Proceedings of the 5th International Workshop on Object Orientation in Operating Systems (IWOOOS '96)
Highly accurate and efficient evaluation of randomising set index functions
Journal of Systems Architecture: the EUROMICRO Journal
Guided region prefetching: a cooperative hardware/software approach
Proceedings of the 30th annual international symposium on Computer architecture
Proceedings of the 30th annual international symposium on Computer architecture
Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
IEEE Transactions on Computers
Execution History Guided Instruction Prefetching
The Journal of Supercomputing
Selective stack prefetch method
CompSysTech '03 Proceedings of the 4th international conference conference on Computer systems and technologies: e-Learning
A new hybrid approach to exploit localities: LRFU with adaptive prefetching
ACM SIGMETRICS Performance Evaluation Review
Self-correcting LRU replacement policies
Proceedings of the 1st conference on Computing frontiers
A first glance at Kilo-instruction based multiprocessors
Proceedings of the 1st conference on Computing frontiers
A virtual server queueing network method for component based performance modelling of metacomputing
Future Generation Computer Systems - Special issue: Semantic grid and knowledge grid: the next-generation web
Coupling compiler-enabled and conventional memory accessing for energy efficiency
ACM Transactions on Computer Systems (TOCS)
Second-Level Buffer Cache Management
IEEE Transactions on Parallel and Distributed Systems
Cluster miss prediction for instruction caches in embedded networking applications
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Power-efficient prefetching via bit-differential offset assignment on embedded processors
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Enhancing data cache reliability by the addition of a small fully-associative replication cache
Proceedings of the 18th annual international conference on Supercomputing
A Content Aware Integer Register File Organization
Proceedings of the 31st annual international symposium on Computer architecture
Profile-directed restructuring of operating system code
IBM Systems Journal
MicroLib: A Case for the Quantitative Comparison of Micro-Architecture Mechanisms
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Toward kilo-instruction processors
ACM Transactions on Architecture and Code Optimization (TACO)
The Impact of Incorrectly Speculated Memory Operations in a Multithreaded Architecture
IEEE Transactions on Parallel and Distributed Systems
Hierarchical Binary Set Partitioning in Cache Memories
The Journal of Supercomputing
Effective Instruction Prefetching via Fetch Prestaging
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
Evaluating kilo-instruction multiprocessors
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
Addressing mode driven low power data caches for embedded processors
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
Comprehensive multiprocessor cache miss rate generation using multivariate models
ACM Transactions on Computer Systems (TOCS)
Branch elimination by condition merging
Software—Practice & Experience
Exploring the limits of prefetching
IBM Journal of Research and Development - Electrochemical technology in microelectronics
The V-Way Cache: Demand Based Associativity via Global Replacement
Proceedings of the 32nd annual international symposium on Computer Architecture
IEEE Transactions on Computers
Memory Performance Optimizations For Real-Time Software HDTV Decoding
Journal of VLSI Signal Processing Systems
Encyclopedia of Computer Science
Replication Cache: A Small Fully Associative Cache to Improve Data Cache Reliability
IEEE Transactions on Computers
MEDEA '04 Proceedings of the 2004 workshop on MEmory performance: DEaling with Applications , systems and architecture
Quantifying Locality In The Memory Access Patterns of HPC Applications
SC '05 Proceedings of the 2005 ACM/IEEE conference on Supercomputing
Studying interactions between prefetching and cache line turnoff
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Kilo-instruction processors, runahead and prefetching
Proceedings of the 3rd conference on Computing frontiers
Exploiting locality to ameliorate packet queue contention and serialization
Proceedings of the 3rd conference on Computing frontiers
Cache miss behavior: is it √2?
Proceedings of the 3rd conference on Computing frontiers
Simple penalty-sensitive replacement policies for caches
Proceedings of the 3rd conference on Computing frontiers
Cache Replacement Algorithms with Nonuniform Miss Costs
IEEE Transactions on Computers
A distributed data caching framework for mobile ad hoc networks
Proceedings of the 2006 international conference on Wireless communications and mobile computing
Statistical sampling of microarchitecture simulation
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Making a case for split data caches for embedded applications
MEDEA '05 Proceedings of the 2005 workshop on MEmory performance: DEaling with Applications , systems and architecture
A PAB-based multi-prefetcher mechanism
International Journal of Parallel Programming
Computation spreading: employing hardware migration to specialize CMP cores on-the-fly
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Reducing energy of virtual cache synonym lookup using bloom filters
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Comprehensive multivariate extrapolation modeling of multiprocessor cache miss rates
ACM Transactions on Computer Systems (TOCS)
Reducing Cache Pollution via Dynamic Data Prefetch Filtering
IEEE Transactions on Computers
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Power-efficient prefetching for embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
I-cache multi-banking and vertical interleaving
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Evolutionary design of en-route caching strategies
Applied Soft Computing
Effectiveness of caching in a distributed digital library system
Journal of Systems Architecture: the EUROMICRO Journal
WCET analysis of instruction caches with prefetching
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Reducing file system latency using a predictive approach
USTC'94 Proceedings of the USENIX Summer 1994 Technical Conference on USENIX Summer 1994 Technical Conference - Volume 1
Exploring the bounds of web latency reduction from caching and prefetching
USITS'97 Proceedings of the USENIX Symposium on Internet Technologies and Systems on USENIX Symposium on Internet Technologies and Systems
Implementation and performance of application-controlled file caching
OSDI '94 Proceedings of the 1st USENIX conference on Operating Systems Design and Implementation
Characteristics of workloads used in high performance and technical computing
Proceedings of the 21st annual international conference on Supercomputing
Web memory hierarchy learning and research environment
WCAE '06 Proceedings of the 2006 workshop on Computer architecture education: held in conjunction with the 33rd International Symposium on Computer Architecture
Optimal multistream sequential prefetching in a shared cache
ACM Transactions on Storage (TOS)
Communications of the ACM
IEEE Transactions on Computers
Strategies for Managing the Register File in RISC
IEEE Transactions on Computers
Estimating the output cardinality of partial preaggregation with a measure of clusteredness
VLDB '03 Proceedings of the 29th international conference on Very large data bases - Volume 29
MEmory performance: DEaling with applications, systems and architecture
ACM SIGARCH Computer Architecture News
Improving SDRAM access energy efficiency for low-power embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Adaptive prefetching algorithm in disk controllers
Performance Evaluation
Design of new XOR-based hash functions for cache memories
Computers & Mathematics with Applications
TaP: table-based prefetching for storage caches
FAST'08 Proceedings of the 6th USENIX Conference on File and Storage Technologies
Tiny split data-caches make big performance impact for embedded applications
Journal of Embedded Computing - Issues in embedded single-chip multicore architectures
Analyzing memory access intensity in parallel programs on multicore
Proceedings of the 22nd annual international conference on Supercomputing
PAM: a novel performance/power aware meta-scheduler for multi-core systems
Proceedings of the 2008 ACM/IEEE conference on Supercomputing
Efficient code caching to improve performance and energy consumption for java applications
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
The VLDB Journal — The International Journal on Very Large Data Bases
Analyzing the worst-case execution time for instruction caches with prefetching
ACM Transactions on Embedded Computing Systems (TECS)
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Measuring the Normality of Web Proxies' Behavior Based on Locality Principles
NPC '08 Proceedings of the IFIP International Conference on Network and Parallel Computing
Synapse tightly coupled multiprocessors: a new approach to solve old problems
AFIPS '84 Proceedings of the July 9-12, 1984, national computer conference and exposition
CMV: File consistency maintenance through virtual servers in peer-to-peer systems
Journal of Parallel and Distributed Computing
Memory resource allocation for file system prefetching: from a supply chain management perspective
Proceedings of the 4th ACM European conference on Computer systems
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Prefetch-Aware DRAM Controllers
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Divide-and-conquer: a bubble replacement for low level caches
Proceedings of the 23rd international conference on Supercomputing
Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE)
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Preventing versus curing: avoiding conflicts in transactional memories
Proceedings of the 28th ACM symposium on Principles of distributed computing
Efficient Data Access Management for FPGA-Based Image Processing SoCs
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
The architecture of the FAIM-1 symbolic multiprocessing system
IJCAI'85 Proceedings of the 9th international joint conference on Artificial intelligence - Volume 1
A load-instruction unit for pipelined processors
IBM Journal of Research and Development
Overview of Multicore Requirements towards Real-Time Communication
SEUS '09 Proceedings of the 7th IFIP WG 10.2 International Workshop on Software Technologies for Embedded and Ubiquitous Systems
A new trace-driven shared-memory multiprocessors machine simulator
International Journal of Computers and Applications
Algorithms for memory hierarchies: advanced lectures
Algorithms for memory hierarchies: advanced lectures
The impact of memory organization on the performance of matrix calculations
Parallel Computing
A refreshing perspective of search engine caching
Proceedings of the 19th international conference on World wide web
Exploiting execution locality with a decoupled Kilo-instruction processor
ISHPC'05/ALPS'06 Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems
Proceedings of the 7th ACM international conference on Computing frontiers
Constructing optimal XOR-functions to minimize cache conflict misses
ARCS'08 Proceedings of the 21st international conference on Architecture of computing systems
LRU-PEA: a smart replacement policy for non-uniform cache architectures on chip multiprocessors
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Mining Query Logs: Turning Search Usage Data into Knowledge
Foundations and Trends in Information Retrieval
Adaptive prefetching for shared cache based chip multiprocessors
Proceedings of the Conference on Design, Automation and Test in Europe
Dynamically reconfigurable cache architecture using adaptive block allocation policy
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Redesigning the string hash table, burst trie, and BST to exploit cache
Journal of Experimental Algorithmics (JEA)
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
Energy-efficient hardware data prefetching
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Partial address directory for cache access
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs
ACM Transactions on Architecture and Code Optimization (TACO)
Using runtime activity to dynamically filter out inefficient data prefetches
Euro-Par'11 Proceedings of the 17th international conference on Parallel processing - Volume Part I
ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
The migration prefetcher: Anticipating data promotion in dynamic NUCA caches
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Working set characterization of applications with an efficient LRU algorithm
EPEW'06 Proceedings of the Third European conference on Formal Methods and Stochastic Models for Performance Evaluation
An effective instruction cache prefetch policy by exploiting cache history information
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
BW-DCache: an inexpensive, effective and reliable cache solution in a SAN file system
HPCS'09 Proceedings of the 23rd international conference on High Performance Computing Systems and Applications
Flux caches: what are they and are they useful?
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Exploration of 3D grid caching strategies for ray-shooting
Journal of Real-Time Image Processing
Soft error mitigation in cache memories of embedded systems by means of a protected scheme
LADC'05 Proceedings of the Second Latin-American conference on Dependable Computing
SAD prefetching for MPEG4 using flux caches
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
A mathematical model for the transitional region between cache hierarchy levels
IICS'04 Proceedings of the 4th international conference on Innovative Internet Community Systems
Extrinsic and intrinsic text cloning
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
Proceedings of the 10th international conference on Mobile systems, applications, and services
A five-level static cache architecture for web search engines
Information Processing and Management: an International Journal
Combining recency of information with selective random and a victim cache in last-level caches
ACM Transactions on Architecture and Code Optimization (TACO)
Accurately modeling superscalar processor performance with reduced trace
Journal of Parallel and Distributed Computing
Replacement techniques for dynamic NUCA cache designs on CMPs
The Journal of Supercomputing
Improving writeback performance of memory-based storage devices
Proceedings of the 8th International Conference on Ubiquitous Information Management and Communication
Computer performance analysis and the Pi Theorem
Computer Science - Research and Development
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