A data cache with multiple caching strategies tuned to different types of locality
ICS '95 Proceedings of the 9th international conference on Supercomputing
A modified approach to data cache management
Proceedings of the 28th annual international symposium on Microarchitecture
Run-time adaptive cache hierarchy management via reference analysis
Proceedings of the 24th annual international symposium on Computer architecture
Memory system characterization of commercial workloads
Proceedings of the 25th annual international symposium on Computer architecture
Active Management of Data Caches by Exploiting Reuse Information
IEEE Transactions on Computers
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
IEEE Transactions on Computers
ACM Computing Surveys (CSUR)
Dead-block prediction & dead-block correlating prefetchers
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
IPDPS '00 Proceedings of the 14th International Symposium on Parallel and Distributed Processing
MEDEA '06 Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures
ACM SIGARCH Computer Architecture News
Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Dueling CLOCK: adaptive cache replacement policy based on the CLOCK algorithm
Proceedings of the Conference on Design, Automation and Test in Europe
Enhancing last-level cache performance by block bypassing and early miss determination
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
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L1 caches must be fast and have a good hit rate at the same time. To be fast, they must remain small. To have a good hit rate, they must be set-associative. With wider associativity the replacement algorithm becomes critical. The wide performance gap between OPT, the optimum off-line algorithm, and LRU suggests that LRU still makes too many mistakes. One way to improve L1 cache behavior is to manage actively the replacement policy to correct these mistakes on the fly.We introduce Self-correcting LRU (SCLRU) which is based on LRU augmented with a feedback loop to constantly monitor and correct replacement mistakes. It relies on several mechanisms to detect, predict, and correct bad replacement decisions. We identify three types of mistakes made by LRU and associate them with memory-access instructions. Our goal is to prevent a mistake to occur more than once. Based on evaluations using a set of seven SPEC95 benchmarks, we show that our approach achieves significant and reliable miss rate improvements, sometimes close to that of OPT, for 2-way and 4-way L1 caches and can do this at a low implementation cost and without affecting the hit cycle time.