Data cache management using frequency-based replacement
SIGMETRICS '90 Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems
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ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
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Proceedings of the 28th annual international symposium on Microarchitecture
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ICS '98 Proceedings of the 12th international conference on Supercomputing
IEEE Transactions on Computers
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ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
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Proceedings of the 1st conference on Computing frontiers
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ICCD '05 Proceedings of the 2005 International Conference on Computer Design
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ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
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Proceedings of the 23rd international conference on Supercomputing
LRU-PEA: a smart replacement policy for non-uniform cache architectures on chip multiprocessors
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Combining recency of information with selective random and a victim cache in last-level caches
ACM Transactions on Architecture and Code Optimization (TACO)
Replacement techniques for dynamic NUCA cache designs on CMPs
The Journal of Supercomputing
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This paper proposes a new replacement algorithm to protect cache lines with potential future reuse from being evicted. In contrast to the recency based approaches used in the past (LRU for example), our algorithm also uses the notion of frequency of access. Instead of evicting the least recently used block, our algorithm identifies among a set of LRU blocks the one that is also least-frequently-used (according to a heuristic) and chooses that as a victim. We have implemented this replacement algorithm in a detailed simulation model of a chip multiprocessor system driven by SPEC2000 benchmarks. We have found that the new scheme improves performance for memory intensive applications. Moreover, as compared to other attempts, our replacement algorithm provides robust improvements across all benchmarks. We have also extended an earlier scheme proposed by Wong and Baer so it is switched off when performance is not improved. Our results show that this makes the scheme much more suitable for CMP configurations.