A Case for Direct-Mapped Caches
Computer
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
An effective on-chip preloading scheme to reduce data access penalty
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
A practical algorithm for exact array dependence analysis
Communications of the ACM
Design and evaluation of a compiler algorithm for prefetching
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Column-associative caches: a technique for reducing the miss rate of direct-mapped caches
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Efficient simulation of caches under optimal replacement with applications to miss characterization
SIGMETRICS '93 Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Evaluating stream buffers as a secondary cache replacement
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
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MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
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IEEE Transactions on Computers - Special issue on cache memory and related problems
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ACM Transactions on Computer Systems (TOCS)
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Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
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PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
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HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
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A study of replacement algorithms for a virtual-storage computer
IBM Systems Journal
Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite
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Journal of Systems Architecture: the EUROMICRO Journal
Counter-Based Cache Replacement Algorithms
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
International Journal of Parallel Programming
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IEEE Transactions on Computers
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Adaptive insertion policies for high performance caching
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P-OPT: Program-Directed Optimal Cache Management
Languages and Compilers for Parallel Computing
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Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with LRU replacement policies to combine fast access with relatively low miss rates. To improve replacement decisions in set-associative caches, we develop a new set of compiler algorithms that predict which data will and will not be reused and provide these hints to the architecture.We prove that the hints either match or improve hit rates over LRU. We describe a practical one-bit cache-line tag implementation of our algorithm, called evict-me. On a cache replacement, the architecture will replace a line for which the evict-me bit is set, or if none is set, it will use the LRU bits. We implement our compiler analysis and its output in the Scale compiler. On a variety of scientific programs, using the evict-me algorithm in both the level 1and 2 caches improves simulated cycle times by up to 34% over the LRU policy by increasing hit rates. In addition, a combination of simple hardware prefetching and evict-me works together to further improve performance.