A study of the performance potential for dynamic instruction hints selection

Authors:
Rao Fu;Jiwei Lu;Antonia Zhai;Wei-Chung Hsu
Affiliations:
Department of Computer Science and Engineering, University of Minnesota;Scalable Systems Group, Sun Microsystems Inc.;Department of Computer Science and Engineering, University of Minnesota;Department of Computer Science and Engineering, University of Minnesota
Venue:
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2006

Citing 8
Cited 0

The SPARC architecture manual (version 9)

The SPARC architecture manual (version 9)
PA-RISC 2.0 architecture

PA-RISC 2.0 architecture
Using the Compiler to Improve Cache Replacement Decisions

Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
64-bit and Multimedia Extensions in the PA-RISC 2.0 Architecture

COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Ispike: A Post-link Optimizer for the Intel®Itanium®Architecture

Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Generating cache hints for improved program efficiency

Journal of Systems Architecture: the EUROMICRO Journal
Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors

Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor

Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture

Quantified Score

Hi-index	0.00

Visualization

Abstract

Instruction hints have become an important way to communicate compile-time information to the hardware. They can be generated by the compiler and the post-link optimizer to reduce cache misses, improve branch prediction and minimize other performance bottlenecks. This paper discusses different instruction hints available on modern processor architectures and shows the potential performance impact on many benchmark programs. Some hints can be effectively selected at compile time with profile feedback. However, since the same program executable can behave differently on various inputs and performance bottlenecks may change on different micro-architectures, significant performance opportunities can be exploited by selecting instruction hints dynamically.