Amortized efficiency of list update and paging rules
Communications of the ACM
Memory bandwidth limitations of future microprocessors
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
An anomaly in space-time characteristics of certain programs running in a paging machine
Communications of the ACM
The hardness of cache conscious data placement
POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Using the Compiler to Improve Cache Replacement Decisions
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Reuse Distance-Based Cache Hint Selection
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
Estimating cache misses and locality using stack distances
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Improving effective bandwidth through compiler enhancement of global cache reuse
Journal of Parallel and Distributed Computing
Generating cache hints for improved program efficiency
Journal of Systems Architecture: the EUROMICRO Journal
Instruction Based Memory Distance Analysis and its Application
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Adaptive insertion policies for high performance caching
Proceedings of the 34th annual international symposium on Computer architecture
Miss Rate Prediction Across Program Inputs and Cache Configurations
IEEE Transactions on Computers
A study of replacement algorithms for a virtual-storage computer
IBM Systems Journal
Evaluation techniques for storage hierarchies
IBM Systems Journal
Minor memory references matter in collaborative caching
Proceedings of the 2011 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness
On the theory and potential of LRU-MRU collaborative cache management
Proceedings of the international symposium on Memory management
Dynamic access distance driven cache replacement
ACM Transactions on Architecture and Code Optimization (TACO)
A generalized theory of collaborative caching
Proceedings of the 2012 international symposium on Memory Management
ViPZonE: OS-level memory variability-driven physical address zoning for energy savings
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Pacman: program-assisted cache management
Proceedings of the 2013 international symposium on memory management
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As the amount of on-chip cache increases as a result of Moore's law, cache utilization is increasingly important as the number of processor cores multiply and the contention for memory bandwidth becomes more severe. Optimal cache management requires knowing the future access sequence and being able to communicate this information to hardware. The paper addresses the communication problem with two new optimal algorithms for Program-directed OPTimal cache management (P-OPT) , in which a program designates certain accesses as bypasses and trespasses through an extended hardware interface to effect optimal cache utilization. The paper proves the optimality of the new methods, examines their theoretical properties, and shows the potential benefit using a simulation study and a simple test on a multi-core, multi-processor PC.