Scheduler-based DRAM energy management
Proceedings of the 39th annual Design Automation Conference
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Impact of Data Transformations on Memory Bank Locality
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Memory access scheduling and binding considering energy minimization in multi-bank memory systems
Proceedings of the 41st annual Design Automation Conference
Dynamic tracking of page miss ratio curve for memory management
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Cooperative Caching with Keep-Me and Evict-Me
INTERACT '05 Proceedings of the 9th Annual Workshop on Interaction between Compilers and Computer Architectures
A performance-conserving approach for reducing peak power consumption in server systems
Proceedings of the 19th annual international conference on Supercomputing
Proceedings of the 43rd annual Design Automation Conference
Process variation aware cache leakage management
Proceedings of the 2006 international symposium on Low power electronics and design
Designing Memory Subsystems Resilient to Process Variations
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Working with process variation aware caches
Proceedings of the conference on Design, automation and test in Europe
Impact of process variations on multicore performance symmetry
Proceedings of the conference on Design, automation and test in Europe
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Variation-aware task allocation and scheduling for MPSoC
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Process Variation Tolerant 3T1D-Based Cache Architectures
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
The PARSEC benchmark suite: characterization and architectural implications
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
P-OPT: Program-Directed Optimal Cache Management
Languages and Compilers for Parallel Computing
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Evaluating memory energy efficiency in parallel I/O workloads
CLUSTER '07 Proceedings of the 2007 IEEE International Conference on Cluster Computing
A durable and energy efficient main memory using phase change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs
IEEE Computer Architecture Letters
Process-Variation-Aware Adaptive Cache Architecture and Management
IEEE Transactions on Computers
Selective wordline voltage boosting for caches to manage yield under process variations
Proceedings of the 46th Annual Design Automation Conference
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy
PRDC '09 Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing
Software adaptation in quality sensitive applications to deal with hardware variability
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Linux Kernel Development
Process variation aware SRAM/cache for aggressive voltage-frequency scaling
Proceedings of the Conference on Design, Automation and Test in Europe
A case for opportunistic embedded sensing in presence of hardware power variability
HotPower'10 Proceedings of the 2010 international conference on Power aware computing and systems
DRAMSim2: A Cycle Accurate Memory System Simulator
IEEE Computer Architecture Letters
ACM SIGARCH Computer Architecture News
Rethinking memory redundancy: optimal bit cell repair for maximum-information storage
Proceedings of the 48th Design Automation Conference
Optimal memory controller placement for chip multiprocessor
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Towards variation-aware system-level power estimation of DRAMs: an empirical approach
Proceedings of the 50th Annual Design Automation Conference
Reliable on-chip systems in the nano-era: lessons learnt and future trends
Proceedings of the 50th Annual Design Automation Conference
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ITRS predicts that over the next decade, hardware power variation will increase at alarming rates. As a result, designers must build software that can adapt to and exploit these variations to reduce power consumption and improve system performance. This paper presents ViPZonE, a system-level solution that opportunistically exploits DRAM power variation through physical address zoning. ViPZonE is composed of a variability-aware software stack that allows developers to indicate to the OS the expected dominant usage patterns (write or read) as well as level of utilization (high, medium, or low) through high-level APIs. ViPZonE's variability-aware page allocator, implemented in the Linux kernel, is responsible for interpreting these high-level requests for memory and transparently mapping them to physical address zones with different power consumption. Our experimental results across various configurations running PAR-SEC workloads show an average of 13.1% memory power consumption savings at the cost of a modest 1.03% increase in execution time over a typical Linux virtual memory allocator.