The gem5 simulator

Authors:
Nathan Binkert;Bradford Beckmann;Gabriel Black;Steven K. Reinhardt;Ali Saidi;Arkaprava Basu;Joel Hestness;Derek R. Hower;Tushar Krishna;Somayeh Sardashti;Rathijit Sen;Korey Sewell;Muhammad Shoaib;Nilay Vaish;Mark D. Hill;David A. Wood
Affiliations:
Hewlett-Packard Labs, Palo Alto, Cal.;Advanced Micro Devices, Inc., Bellevue, Wash;Google, Inc., Mountain View, Cal.;Advanced Micro Devices, Inc., Bellevue, Wash;ARM, Inc., Austin, Tex.;University of Wisconsin, Madison, Wisc.;University of Texas, Austin, Tex.;University of Wisconsin, Madison, Wisc.;Massachusetts Institute of Technology, Cambridge, Mass.;University of Wisconsin, Madison, Wisc.;University of Wisconsin, Madison, Wisc.;University of Michigan, Ann Arbor;University of Wisconsin, Madison, Wisc.;University of Wisconsin, Madison, Wisc.;University of Wisconsin, Madison, Wisc.;University of Wisconsin, Madison, Wisc.
Venue:
ACM SIGARCH Computer Architecture News
Year:
2011

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Abstract

The gem5 simulation infrastructure is the merger of the best aspects of the M5 [4] and GEMS [9] simulators. M5 provides a highly configurable simulation framework, multiple ISAs, and diverse CPU models. GEMS complements these features with a detailed and exible memory system, including support for multiple cache coherence protocols and interconnect models. Currently, gem5 supports most commercial ISAs (ARM, ALPHA, MIPS, Power, SPARC, and x86), including booting Linux on three of them (ARM, ALPHA, and x86). The project is the result of the combined efforts of many academic and industrial institutions, including AMD, ARM, HP, MIPS, Princeton, MIT, and the Universities of Michigan, Texas, and Wisconsin. Over the past ten years, M5 and GEMS have been used in hundreds of publications and have been downloaded tens of thousands of times. The high level of collaboration on the gem5 project, combined with the previous success of the component parts and a liberal BSD-like license, make gem5 a valuable full-system simulation tool.