TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration

Authors:
Matthias Jung;Christian Weis;Norbert Wehn;Karthik Chandrasekar
Affiliations:
University of Kaiserslautern, Germany;University of Kaiserslautern, Germany;University of Kaiserslautern, Germany;Delft University of Technology, Netherlands
Venue:
Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
Year:
2013

Citing 11
Cited 0

Hitting the memory wall: implications of the obvious

ACM SIGARCH Computer Architecture News
The SimpleScalar tool set, version 2.0

ACM SIGARCH Computer Architecture News
Transaction level modeling: an overview

Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs

Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
SystemC: From the Ground Up, Second Edition

SystemC: From the Ground Up, Second Edition
An efficient distributed memory interface for many-core platform with 3D stacked DRAM

Proceedings of the Conference on Design, Automation and Test in Europe
DRAMSim2: A Cycle Accurate Memory System Simulator

IEEE Computer Architecture Letters
Pinned to the walls: impact of packaging and application properties on the memory and power walls

Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
The gem5 simulator

ACM SIGARCH Computer Architecture News
Improved Power Modeling of DDR SDRAMs

DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
Heterogeneous multi-channel: fine-grained DRAM control for both system performance and power efficiency

Proceedings of the 49th Annual Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

Three-dimensional stacked Wide I/O DRAMs have been proposed as a promising solution to overcome the pin-limited memory performance growth, the power vs. bandwidth dilemma and the Memory Wall. This new DRAM architecture and organisation requires a new generation of DRAM memory controllers. In this paper, we present a new methodology using virtual platforms to model the backend of a 3D-DRAM memory subsystem (channel controller and Wide I/O DRAM) with special SystemC TLM2.0 phase extensions. This methodology enables us to explore the complete design space of memory controllers at the system level at very fast simulation speeds with precise timing accuracy. We show simulation speedups of up to 377x with a timing accuracy of 99% compared to an equivalent cycle and pin accurate SystemC based RTL simulation.