Run-time power-down strategies for real-time SDRAM memory controllers
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs
Proceedings of the Conference on Design, Automation and Test in Europe
XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs
Proceedings of the 50th Annual Design Automation Conference
Towards variation-aware system-level power estimation of DRAMs: an empirical approach
Proceedings of the 50th Annual Design Automation Conference
DRAM selection and configuration for real-time mobile systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Memory-map selection for firm real-time SDRAM controllers
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Power modeling and estimation has become one of the most defining aspects in designing modern embedded systems. In this context, DDR SDRAM memories contribute significantly to system power consumption, but lack accurate and generic power models. The most popular SDRAM power model provided by Micron, is found to be inaccurate or insufficient for several reasons. First, it does not consider the power consumed when transitioning to power-down and self-refresh modes. Second, it employs the minimal timing constraints between commands from the SDRAM datasheets and not the actual duration between the commands as issued by an SDRAM memory controller. Finally, without adaptations, it can only be applied to a memory controller that employs a close-page policy and accesses a single SDRAM bank at a time. These critical issues with Micron's power model impact the accuracy and the validity of the power values reported by it and resolving them, forms the focus of our work. In this paper, we propose an improved SDRAM power model that estimates power consumption during the state transitions to power-saving states, employs an SDRAM command trace to get the actual timings between the commands issued and is generic and applicable to all DDRx SDRAMs and all memory controller policies and all degrees of bank interleaving. We quantitatively compare the proposed model against the unmodified Micron model on power and energy for DDR3-800. We show differences of up to 60% in energy-savings for the precharge power-down mode for a power-down duration of 14 cycles and up to 80% for the self-refresh mode for a self-refresh duration of 560 cycles.