ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Predator: a predictable SDRAM memory controller
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Memory Systems: Cache, DRAM, Disk
Memory Systems: Cache, DRAM, Disk
Performance analysis of multi-channel memories in mobile devices
SOC'09 Proceedings of the 11th international conference on System-on-chip
3D Stacked Microprocessor: Are We There Yet?
IEEE Micro
System-level power/performance evaluation of 3D stacked DRAMs for mobile applications
Proceedings of the Conference on Design, Automation and Test in Europe
A case for multi-channel memories in video recording
Proceedings of the Conference on Design, Automation and Test in Europe
Heterogeneous multi-core platform for consumer multimedia applications
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Classification and Analysis of Predictable Memory Patterns
RTCSA '10 Proceedings of the 2010 IEEE 16th International Conference on Embedded and Real-Time Computing Systems and Applications
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
PRET DRAM controller: bank privatization for predictability and temporal isolation
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Improved Power Modeling of DDR SDRAMs
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
Mobile system considerations for SDRAM interface trends
Proceedings of the System Level Interconnect Prediction Workshop
An Analyzable Memory Controller for Hard Real-Time CMPs
IEEE Embedded Systems Letters
Memory-map selection for firm real-time SDRAM controllers
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs
Proceedings of the Conference on Design, Automation and Test in Europe
Architecture and optimal configuration of a real-time multi-channel memory controller
Proceedings of the Conference on Design, Automation and Test in Europe
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The performance and power consumption of mobile DRAMs (LPDDRs) depend on the configuration of system-level parameters, such as operating frequency, interface width, request size, and memory map. In mobile systems running both real-time and non-real-time applications, the memory configuration must satisfy bandwidth requirements of real-time applications, meet the power consumption budget, and offer the best average-case execution time to the non-real-time applications. There is currently no well-defined methodology for selecting a suitable memory configuration for real-time mobile systems. The worst-case bandwidth, average-case execution time, and power consumption of mobile DRAMs across generations have furthermore not been investigated. This paper has two main contributions. 1) We analyze the worst-case bandwidth, average-case execution time, and power consumption of mobile DRAMs across three generations: LPDDR, LPDDR2 and Wide-IO-based 3D-stacked DRAM. 2) Based on our analysis, we propose a methodology for selecting memory configurations in real-time mobile systems. We show that LPDDR (32-bit IO), LPDDR2 (32-bit IO) and 3D-DRAM (128-bit IO) provide worst-case bandwidth up to 0.75 GB/s, 1.6 GB/s and 3.1 GB/s, respectively. We furthermore show for an H.263 decoder that LPDDR2 and 3D-DRAM reduce power consumption with up to 25% and 67%, respectively, compared to LPDDR, and reduce the execution time with up to 18% and 25%.