Digital systems engineering
Three-Dimensional Cache Design Exploration Using 3DCacti
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Power-centric design of high-speed I/Os
Proceedings of the 43rd annual Design Automation Conference
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
CACTI-IO: CACTI with off-chip power-area-timing models
Proceedings of the International Conference on Computer-Aided Design
DRAM selection and configuration for real-time mobile systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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A variety of interconnect technologies and standards (DIMMs, MCP, POP, stacked-die and 3D-stack) enable a controller IC to communicate with an external SDRAM, or with multiple SDRAMs over a shared interconnect. Low-power requirements have driven mobile controllers to mobile-SDRAM (LPDDR) memory solutions. However, LPDDR configurations do not scale to match the throughput and capacity requirements of mobile processors, or of emerging tablet products that bring new and divergent tradeoffs among memory subsystem metrics. As a result, identifying the memory configuration best suited to a given mobile application becomes quite challenging. This paper highlights considerations in choosing a particular memory configuration for a mobile processor based on capacity, throughput, latency, power, cost and thermal concerns. We distinguish various choices according to interconnect implementation and performance, including power and timing in the IO and interconnect. To do this, we apply a three-part framework: (1) driving questions in the form of a decision tree, (2) a calculator that projects power and timing for mobile IO implementations, and (3) propagated top-down requirements and bottom-up capabilities that distinguish interconnect implementations. Our framework can support abstraction of timing and power for various interconnect configurations, to feed higher-level tools such as CACTI [19]. We anticipate that it can also be used to project mobile system requirements and memory interconnect capabilities into the future, so as to identify any gaps or bottlenecks in memory product roadmaps.