Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Proceedings of the 27th annual international symposium on Computer architecture
DRAM Circuit Design: A Tutorial
DRAM Circuit Design: A Tutorial
Designing and Programming the Emotion Engine
IEEE Micro
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Logic-based eDRAM: origins and rationale for use
IBM Journal of Research and Development - Electrochemical technology in microelectronics
Three-Dimensional Cache Design Exploration Using 3DCacti
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Implementing Caches in a 3D Technology for High Performance Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)
Proceedings of the 2006 international symposium on Low power electronics and design
PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Die Stacking (3D) Microarchitecture
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Design and integration methods for a multi-threaded dual core 65nm Xeon® processor
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Embedded DRAM: technology platform for the Blue Gene/L chip
IBM Journal of Research and Development
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
COTSon: infrastructure for full system simulation
ACM SIGOPS Operating Systems Review
A durable and energy efficient main memory using phase change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
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Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 20th symposium on Great lakes symposium on VLSI
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Proceedings of the 37th annual international symposium on Computer architecture
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support
Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
Understanding the Energy Consumption of Dynamic Random Access Memories
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Moguls: a model to explore the memory hierarchy for bandwidth improvements
Proceedings of the 38th annual international symposium on Computer architecture
A study on factors influencing power consumption in multithreaded and multicore CPUs
WSEAS Transactions on Computers
Dynamic access distance driven cache replacement
ACM Transactions on Architecture and Code Optimization (TACO)
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Proceedings of the 48th Design Automation Conference
Demand Paging Techniques for Flash Memory Using Compiler Post-Pass Optimizations
ACM Transactions on Embedded Computing Systems (TECS)
A Green Parallel Forwarding and Switching Architecture for Green Network
GREENCOM '11 Proceedings of the 2011 IEEE/ACM International Conference on Green Computing and Communications
Proceedings of the International Conference on Computer-Aided Design
Improving System Energy Efficiency with Memory Rank Subsetting
ACM Transactions on Architecture and Code Optimization (TACO)
Mobile system considerations for SDRAM interface trends
Proceedings of the System Level Interconnect Prediction Workshop
CRAM: coded registers for amplified multiporting
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Memory power optimization of Java-based embedded systems exploiting garbage collection information
Journal of Systems Architecture: the EUROMICRO Journal
Scalable memory hierarchies for embedded manycore systems
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Versatile refresh: low complexity refresh scheduling for high-throughput multi-banked eDRAM
Proceedings of the 12th ACM SIGMETRICS/PERFORMANCE joint international conference on Measurement and Modeling of Computer Systems
Instruction-based energy estimation methodology for asymmetric manycore processor simulations
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Power-aware performance increase via core/uncore reinforcement control for chip-multiprocessors
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
A case for exploiting subarray-level parallelism (SALP) in DRAM
Proceedings of the 39th Annual International Symposium on Computer Architecture
Combining recency of information with selective random and a victim cache in last-level caches
ACM Transactions on Architecture and Code Optimization (TACO)
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Proceedings of the 21st international conference on Parallel architectures and compilation techniques
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CACTI-IO: CACTI with off-chip power-area-timing models
Proceedings of the International Conference on Computer-Aided Design
Towards a performance- and energy-efficient data filter cache
Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems
ACM Transactions on Architecture and Code Optimization (TACO)
Phase-change memory: An architectural perspective
ACM Computing Surveys (CSUR)
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OAP: an obstruction-aware cache management policy for STT-RAM last-level caches
Proceedings of the Conference on Design, Automation and Test in Europe
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Proceedings of the 40th Annual International Symposium on Computer Architecture
GPUWattch: enabling energy optimizations in GPGPUs
Proceedings of the 40th Annual International Symposium on Computer Architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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SC '13 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
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E2SC '13 Proceedings of the 1st International Workshop on Energy Efficient Supercomputing
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ACM Transactions on Architecture and Code Optimization (TACO)
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ACM Transactions on Architecture and Code Optimization (TACO)
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In this paper we introduce CACTI-D, a significant enhancement of CACTI 5.0. CACTI-D adds support for modeling of commodity DRAM technology and support for main memory DRAM chip organization. CACTI-D enables modeling of the complete memory hierarchy with consistent models all the way from SRAM based L1 caches through main memory DRAMs on DIMMs. We illustrate the potential applicability of CACTI-D in the design and analysis of future memory hierarchies by carrying out a last level cache study for a multicore multithreaded architecture at the 32nm technology node. In this study we use CACTI-D to model all components of the memory hierarchy including L1, L2, last level SRAM, logic process based DRAM or commodity DRAM L3 caches, and main memory DRAM chips. We carry out architectural simulation using benchmarks with large data sets and present results of their execution time, breakdown of power in the memory hierarchy, and system energy-delay product for the different system configurations. We find that commodity DRAM technology is most attractive for stacked last level caches, with significantly lower energy-delay products.