Demand Paging Techniques for Flash Memory Using Compiler Post-Pass Optimizations

  • Authors:

  • Seungkyun Kim;Kiwon Kwon;Chihun Kim;Choonki Jang;Jaejin Lee;Sang Lyul Min

  • Affiliations:

  • Seoul National University;QUALCOMM Korea;NEXON Co.;Seoul National University;Seoul National University;Seoul National University

  • Venue:
  • ACM Transactions on Embedded Computing Systems (TECS)
  • Year:
  • 2011

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Abstract

In this article, we propose an application-specific demand paging mechanism for low-end embedded systems that have flash memory as secondary storage. These systems are not equipped with virtual memory. A small memory space called an execution buffer is used to page the code of an application. An application-specific page manager manages the buffer. The page manager is automatically generated by a compiler post-pass optimizer and combined with the application image. The post-pass optimizer analyzes the executable image and transforms function call/return instructions into calls to the page manager. As a result, each function in the code can be loaded into the memory on demand at runtime. To minimize the overhead incurred by the demand paging technique, code clustering algorithms are also presented. We evaluate our techniques with ten embedded applications, and our approach can reduce the code memory size by on average 39.5% with less than 10% performance degradation and on average 14% more energy consumption. Our demand paging technique provides embedded system designers with a trade-off control mechanism between the cost, performance, and energy efficiency in designing embedded systems. Embedded system designers can choose the code memory size depending on their cost, energy, and performance requirements.