CACTI-P: architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques

Authors:
Sheng Li;Ke Chen;Jung Ho Ahn;Jay B. Brockman;Norman P. Jouppi
Affiliations:
Hewlett-Packard Labs;Hewlett-Packard Labs, and University of Notre Dame;Seoul National University;University of Notre Dame;Hewlett-Packard Labs
Venue:
Proceedings of the International Conference on Computer-Aided Design
Year:
2011

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Abstract

This paper introduces CACTI-P, the first architecture-level integrated power, area, and timing modeling framework for SRAM-based structures with advanced leakage power reduction techniques. CACTI-P supports modeling of major leakage power reduction approaches including power-gating, long channel devices, and Hi-k metal gate devices. Because it accounts for implementation overheads, CACTI-P enables in-depth study of architecture-level tradeoffs for advanced leakage power management schemes. We illustrate the potential applicability of CACTI-P in the design and analysis of leakage power reduction techniques of future manycore processors by applying nanosecond scale power-gating to different levels of cache for a 64 core multithreaded architecture at the 22nm technology. Combining results from CACTI-P and a performance simulator, we find that although nanosecond scale power-gating is a powerful way to minimize leakage power for all levels of caches, its severe impacts on processor performance and energy when being used for L1 data caches make nanosecond scale power-gating a better fit for caches closer to main memory.