SPEC CPU suite growth: an historical perspective
ACM SIGARCH Computer Architecture News
Subsetting the SPEC CPU2006 benchmark suite
ACM SIGARCH Computer Architecture News
ACM SIGARCH Computer Architecture News
Subroutine profiling results for the CPU2006 benchmarks
ACM SIGARCH Computer Architecture News
Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite
Proceedings of the 34th annual international symposium on Computer architecture
Future scaling of processor-memory interfaces
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Algorithms and data structures for massively parallel generic adaptive finite element codes
ACM Transactions on Mathematical Software (TOMS)
System implications of memory reliability in exascale computing
Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis
Proceedings of the International Conference on Computer-Aided Design
Improving System Energy Efficiency with Memory Rank Subsetting
ACM Transactions on Architecture and Code Optimization (TACO)
ACM Transactions on Architecture and Code Optimization (TACO)
Improving virtualization in the presence of software managed translation lookaside buffers
Proceedings of the 40th Annual International Symposium on Computer Architecture
| Hi-index | 0.00 |
Performance counters provide the means to track detailed events that occur on a CPU chip. These events are of interest to both performance analysts and compiler developers. Counting them provides essential clues to guide performance improvement. For example, a tester who sees that a program has a high cache miss rate on a particular system may experiment with compilation options that improve prefetching. A compiler developer who sees the same thing may realize that the code generator's machine model is missing some crucial detail of behavior on that particular system.