MTCMOS hierarchical sizing based on mutual exclusive discharge patterns

Authors:
James Kao;Siva Narendra;Anantha Chandrakasan
Affiliations:
Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology;Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology;Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology
Venue:
DAC '98 Proceedings of the 35th annual Design Automation Conference
Year:
1998

Citing 3
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Abstract

Multi-threshold CMOS is a popular circuit style that will provide high performance and low power operation. Optimally sizing the gating sleep transistor to provide adequate performance is difficult because the overall delay characteristics are strongly dependent on the discharge patterns of internal gates. This paper proposes a methodology for sizing the sleep transistor for a large module based on mutual exclusive discharge patterns of internal blocks. This algorithm can be applied at all levels of a circuit hierarchy, where the internal blocks can represent transistors, cells within an array, or entire modules. This methodology will give an upper bound for the sleep transistor size required to meet any performance constraint.