Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application

Authors:
B. Chung;J. B. Kuo
Affiliations:
School of Engineering Science, SFU, Burnaby, Canada V5A 1S5;School of Engineering Science, SFU, Burnaby, Canada V5A 1S5
Venue:
Integration, the VLSI Journal
Year:
2008

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Abstract

Thermal gradients across the die are becoming increasingly prominent as we scale further down into the sub-nanometer regime. While temperature was never a primary concern, its non-negligible impact on delay and reliability is getting significant attention ...