Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits

Authors:
Debasis Samanta;Ajit Pal
Affiliations:
Department of Computer Science & Engineering, Indian Institute of Technology Kharagpur, India;Department of Computer Science & Engineering, Indian Institute of Technology Kharagpur, India
Venue:
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Year:
2002

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Abstract

In this paper we have addressed the problem of realizing dual-VT CMOS circuits for battery-operated hand held and portable systems. As the battery life is of primary concern, an algorithm is proposed to realize circuits with near minimal energy requirement in the standby mode as well as in the active mode, at the expense of some performance. An efficient algorithm for dual-VT assignment has been developed, which assigns high-VT to larger number of transistors compared to the existing approaches, leading to higher reduction in power. Experiments have been carried out to study the reduction in power requirement with the increase in delay (with corresponding increase in low-VT) compared to the highest performance single-VT realization. Our algorithm has been tested using standard ISCAS benchmark circuits. Experimental results have established that, by compromising small performance (5 to 10% increase in delay), it is possible to realize CMOS circuits using dual-VT technology with near-minimal energy requirement.